Inventor · disambiguated record
Paul A. Ronsheim
Also filed as: PLETTNER CRISTINA · RONSHEIM PAUL · RONSHEIM PAUL A · RONSHEIM PAUL ANDREW
18 granted patents·5 pending applications·476 citations·filing 1991–2012
95Inventor score
Top patents by PatentIndex Score
23 records- 0196US7071103B2Chemical treatment to retard diffusion in a semiconductor overlayerIBM·Filed 2004·Granted Jul 4, 2006·120 cites·25 claims
- 0290US5656514AMethod for making heterojunction bipolar transistor with self-aligned retrograde emitter profileIBM·Filed 1994·Granted Aug 12, 1997·96 cites·8 claims
- 0389US8900973B2Method to enable compressively strained pFET channel in a FinFET structure by implant and thermal diffusionBERLINER NATHANIEL C·Filed 2011·Granted Dec 2, 2014·14 cites·18 claims
- 0485US6509241B2Process for fabricating an MOS device having highly-localized halo regionsIBM·Filed 2000·Granted Jan 21, 2003·35 cites·19 claims
- 0579US5194397AMethod for controlling interfacial oxide at a polycrystalline/monocrystalline silicon interfaceIBM·Filed 1991·Granted Mar 16, 1993·76 cites·23 claims
- 0677US6335262B1Method for fabricating different gate oxide thicknesses within the same chipIBM·Filed 1999·Granted Jan 1, 2002·46 cites·8 claims
- 0775US6749684B1Method for improving CVD film quality utilizing polysilicon gettererIBM·Filed 2003·Granted Jun 15, 2004·11 cites·19 claims
- 0872US8114748B2Shallow extension regions having abrupt extension junctionsLEE KAM-LEUNG·Filed 2009·Granted Feb 14, 2012·5 cites·16 claims
- 0972US6329704B1Ultra-shallow junction dopant layer having a peak concentration within a dielectric layerIBM·Filed 1999·Granted Dec 11, 2001·34 cites·7 claims
- 1069US6635517B2Use of disposable spacer to introduce gettering in SOI layerIBM·Filed 2001·Granted Oct 21, 2003·13 cites·25 claims
- 1165US9099461B2Method of manufacturing scaled equivalent oxide thickness gate stacks in semiconductor devices and related design structureCHUDZIK MICHAEL P·Filed 2012·Granted Aug 4, 2015·1 cites·15 claims
- 1260US6387782B2Process of forming an ultra-shallow junction dopant layer having a peak concentration within a dielectric layerIBM·Filed 2001·Granted May 14, 2002·6 cites·15 claims
- 1358US8158449B2Particle emission analysis for semiconductor fabrication stepsCABRAL JR CYRIL·Filed 2008·Granted Apr 17, 2012·1 cites·15 claims
- 1446US6399434B1Doped structures containing diffusion barriersIBM·Filed 2000·Granted Jun 4, 2002·3 cites·7 claims
- 1540US6194736B1Quantum conductive recrystallization barrier layersIBM·Filed 1998·Granted Feb 27, 2001·8 cites·31 claims
- 1639US2008311732A1Method for Forming Non-Amorphous, Ultra-Thin Semiconductor Devices Using Sacrificial Implantation LayerIBM·Filed 2003·Application pending·0 cites
- 1739US2003094660A1Method for fabricating different gate oxide thickness within the same chipFiled 2001·Application pending·0 cites
- 1838US8347741B2Specimen handling apparatusIBM·Filed 2010·Granted Jan 8, 2013·0 cites·19 claims
- 1938US2012190216A1Annealing techniques for high performance complementary metal oxide semiconductor (cmos) device fabricationCHAN KEVIN K·Filed 2011·Application pending·0 cites
- 2033US6114257AProcess for modified oxidation of a semiconductor substrate using chlorine plasmaIBM·Filed 1998·Granted Sep 5, 2000·4 cites·15 claims
- 2133US2002177264A1Reducing threshold voltage roll-up/roll-off effect for MOSFETSIBM·Filed 2001·Application pending·0 cites
- 2230US5385850AMethod of forming a doped region in a semiconductor substrate utilizing a sacrificial epitaxial silicon layerIBM·Filed 1991·Granted Jan 31, 1995·3 cites·9 claims
- 2328US2012117696A1Integrated metallic microtip coupon structure for atom probe tomographic analysisHATZISTERGOS MICHAEL·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →