Inventor · disambiguated record

Paul G. G. Vanloon

Also filed as: YIM ERNEST W

2 granted patents·51 citations·filing 1975–1977

65Inventor score

Technology areasH10W

Files withSILICONIX INC2

Top patents by PatentIndex Score

2 records

0177US4161417AMethod of making CMOS structure with retarded electric field for minimum latch-upSILICONIX INC·Filed 1977·Granted Jul 17, 1979·40 cites·2 claims
0245US4203126ACMOS structure and method utilizing retarded electric field for minimum latch-upSILICONIX INC·Filed 1975·Granted May 13, 1980·11 cites·6 claims

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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →