Inventor · disambiguated record
Padmanabha Venkitakrishnan
Also filed as: VENKITAKRISHNAN PADMANABHA · VENKITAKRISHNAN PADMANABHA I
9 granted patents·2 pending applications·317 citations·filing 1985–2005
91Inventor score
Files withHEWLETT PACKARD CO4HEWLETT PACKARD DEVELOPMENT CO3ADVANCED MICRO DEVICES INC1HENZE RICHARD H1HEWLETT PACKARD DEVELOPMENT LP1
Top patents by PatentIndex Score
11 records- 0185US6513145B1Method for estimating the power consumed in a microprocessorHEWLETT PACKARD CO·Filed 2001·Granted Jan 28, 2003·46 cites·21 claims
- 0282US6918012B2Streamlined cache coherency protocol system and method for a multiple processor single chip deviceHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Jul 12, 2005·38 cites·16 claims
- 0374US6378029B1Scalable system control unit for distributed shared memory multi-processor systemsHEWLETT PACKARD CO·Filed 1999·Granted Apr 23, 2002·70 cites·20 claims
- 0472US7003441B2Method for deriving the benchmark program for estimating the maximum power consumed in a microprocessorHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Feb 21, 2006·19 cites·10 claims
- 0568US6374331B1Distributed directory cache coherence multi-processor computer architectureHEWLETT PACKARD CO·Filed 1998·Granted Apr 16, 2002·56 cites·18 claims
- 0662US6874014B2Chip multiprocessor with multiple operating systemsHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Mar 29, 2005·12 cites·19 claims
- 0757US6597692B1Scalable, re-configurable crossbar switch architecture for multi-processor system interconnection networksHEWLETT PACKARD DEVELOPMENT LP·Filed 1999·Granted Jul 22, 2003·19 cites·16 claims
- 0857US6263415B1Backup redundant routing system crossbar switch architecture for multi-processor system interconnection networksHEWLETT PACKARD CO·Filed 1999·Granted Jul 17, 2001·40 cites·19 claims
- 0949US4641247ABit-sliced, dual-bus design of integrated circuitsADVANCED MICRO DEVICES INC·Filed 1985·Granted Feb 3, 1987·17 cites·8 claims
- 1040US2003023794A1Cache coherent split transaction memory bus architecture and protocol for a multi processor chip deviceFiled 2001·Application pending·0 cites
- 1137US2006190552A1Data retention system with a plurality of access protocolsHENZE RICHARD H·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →