Method for estimating the power consumed in a microprocessor

Abstract

In one embodiment, the present invention provides a method for estimating the maximum power consumed in a microprocessor or other architecture, at an architectural level, prior to implementation. A functional model represents the architecture at a high level of abstraction. In one embodiment, the model is written in SystemC. In one embodiment, power consumption is expressed power weights, derived by reference to architecture technology. In one embodiment, a method of estimating power consumption prior to implementation operates by modeling a benchmark, compiling it into an instruction stream, assigning power weights for each stage of each architectural function, running the model in a maximum power consumption mode, and summarizing the resulting power consumption. In one embodiment, a PERL script compiler is used. In one embodiment, the power weights are calculated corresponding to the characteristic architecture technology. In one embodiment, a power virus program runs the model in the maximum power mode.

What is claimed is:  
     
       1. A method for generating a functional model of an electronic architecture, said architecture having a functional constitution, said method comprising: 
       representing said functional constitution at a high level of abstraction;  
       simulating the operation of said functional constitution;  
       modeling a power consumption value of said functional constitution in terms of maximum power; and  
       projecting a corresponding power consumption attribute upon said architecture.  
     
     
       2. The method as recited in  claim 1 , wherein said representing said functional constitution at a high level of abstraction further comprises modeling said functional constitution in SystemC. 
     
     
       3. The method as recited in  claim 1 , wherein said architecture is a microprocessor architecture. 
     
     
       4. The method as recited in  claim 1 , wherein said architecture is an integrated circuit architecture. 
     
     
       5. The method as recited in  claim 4 , wherein said integrated circuit architecture is an application specific integrated circuit architecture. 
     
     
       6. The method as recited in  claim 4 , wherein said integrated circuit architecture is a microcontroller architecture. 
     
     
       7. The method as recited in  claim 1 , wherein said architecture is a system architecture. 
     
     
       8. The method as recited in  claim 7 , wherein said system architecture is a computer system architecture. 
     
     
       9. The method as recited in  claim 1 , wherein said power consumption of said functional constitution of said architecture is expressed in terms of power weight, said power weight derived by reference to a technology constituting said functional constitution. 
     
     
       10. For an electronic architecture with a functional constitution, said functional constitution performing a number of architectural functions characterized by separate stages, a method of estimating a power consumption prior to an implementation of said architecture, said method comprising: 
       modeling a functional model of said architecture;  
       compiling a benchmark program into a corresponding instruction stream;  
       adding a power weight for each said stage of each said function;  
       running said model in a maximum power consumption mode; and  
       summarizing said power consumption.  
     
     
       11. The method as recited in  claim 10 , wherein said functional model comprises a representation of said functional constitution of said architecture at a high level of abstraction capable of simulating the functioning of said architecture and said functional constitution thereof, the total power consumption of said architecture and of said functional constitution thereof, wherein said power consumption is in terms of maximum power. 
     
     
       12. The method as recited in  claim 11 , wherein said modeling a functional model of said architecture further comprises writing a program in SystemC. 
     
     
       13. The method as recited in  claim 10 , wherein said compiling a benchmark program into a corresponding instruction stream is performed by a compiler. 
     
     
       14. The method as recited in  claim 13 , wherein said compiler is a PERL script. 
     
     
       15. The method as recited in  claim 10 , wherein said adding a power weight for each said stage of each said function further comprises: 
       selecting each of said architectural functions individually; determining the characteristic technology of each of said architectural functions selected;  
       counting a number of technology gates constituting each of said architectural functions selected;  
       determining a power weight for each of said technology gates; and  
       deriving a power weight for each of said architectural functions selected.  
     
     
       16. The method as recited in  claim 15 , wherein said selecting each of said architectural functions individually further comprises: 
       determining if said architectural functions selected are memory type functions;  
       itemizing individual memory subfunctions; and  
       treating each of said individual memory subfunctions as separate, equivalent, distinct architectural functions.  
     
     
       17. The method as recited in  claim 15  wherein said deriving a power weight for each of said architectural functions selected comprises multiplying said power weight determined for each of said technology gates by said number of said technology gates. 
     
     
       18. The method as recited in  claim 10 , wherein said summarizing said power consumption further comprises running a power virus program. 
     
     
       19. The method as recited in  claim 10 , wherein said architecture is a microprocessor. 
     
     
       20. The method as recited in  claim 10 , wherein said architecture is an integrated circuit. 
     
     
       21. The method as recited in  claim 20 , wherein said architecture is an application specific integrated circuit.