Inventor · disambiguated record
Patrick M. Williams
Also filed as: WILLIAMS PATRICK · WILLIAMS PATRICK M
17 granted patents·2 pending applications·398 citations·filing 1998–2023
94Inventor score
Top patents by PatentIndex Score
19 records- 0195US7093208B2Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devicesIBM·Filed 2004·Granted Aug 15, 2006·234 cites·17 claims
- 0285US7627836B2OPC trimming for performanceIBM·Filed 2005·Granted Dec 1, 2009·15 cites·7 claims
- 0385US7325210B2Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnectIBM·Filed 2005·Granted Jan 29, 2008·17 cites·13 claims
- 0484US7010763B2Method of optimizing and analyzing selected portions of a digital integrated circuitIBM·Filed 2003·Granted Mar 7, 2006·38 cites·1 claims
- 0583US7971171B2Method and system for electromigration analysis on signal wiringIBM·Filed 2008·Granted Jun 28, 2011·13 cites·22 claims
- 0681US10360338B2Method for improving capacitance extraction performance by approximating the effect of distant shapesIBM·Filed 2016·Granted Jul 23, 2019·5 cites·9 claims
- 0777US10565336B2Pessimism reduction in cross-talk noise determination used in integrated circuit designIBM·Filed 2018·Granted Feb 18, 2020·3 cites·12 claims
- 0875US10248753B2Pessimism reduction in hierarchical blockage aggressors using estimated resistor and capacitor valuesIBM·Filed 2016·Granted Apr 2, 2019·2 cites·20 claims
- 0973US7003747B2Method of achieving timing closure in digital integrated circuits by optimizing individual macrosIBM·Filed 2003·Granted Feb 21, 2006·15 cites·1 claims
- 1071US7743355B2Method of achieving timing closure in digital integrated circuits by optimizing individual macrosIBM·Filed 2007·Granted Jun 22, 2010·4 cites·12 claims
- 1167US8239804B2Method for calculating capacitance gradients in VLSI layouts using a shape processing engineELFADEL IBRAHIM M·Filed 2009·Granted Aug 7, 2012·4 cites·19 claims
- 1264US10254784B1Using required arrival time constraints for coupled noise analysis and noise aware timing analysis of out-of-context (OOC) hierarchical entitiesIBM·Filed 2018·Granted Apr 9, 2019·1 cites·20 claims
- 1355US10552570B2Pessimism reduction in hierarchical blockage aggressors using estimated resistor and capacitor valuesIBM·Filed 2018·Granted Feb 4, 2020·0 cites·20 claims
- 1450US6629298B1Automated programmable process and method for the improvement of electrical digital signal transition rates in a VLSI designIBM·Filed 1999·Granted Sep 30, 2003·24 cites·16 claims
- 1549US6022231APre-bussed rigid conduit electrical distribution systemSQUARE D CO·Filed 1998·Granted Feb 8, 2000·19 cites·25 claims
- 1649US2006150127A1Method of achieving timing closure in digital integrated circuits by optimizing individual macrosIBM·Filed 2005·Application pending·0 cites
- 1749US2024353642A1Nestable enclosure kit and enclosure assembly for telecommunication cablePLUGIN OPTICS INC·Filed 2023·Application pending·0 cites
- 1845US10169514B2Approximation of resistor-capacitor circuit extraction for thread-safe design changesIBM·Filed 2017·Granted Jan 1, 2019·0 cites·20 claims
- 1928US6176719B1Bolted electrical connecting device for multiple electrical conductorsSQUARE D CO·Filed 1998·Granted Jan 23, 2001·4 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →