Method of achieving timing closure in digital integrated circuits by optimizing individual macros

Abstract

Disclosed is a method for enhanced efficiency and effectiveness in achieving closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.

1 . A method of achieving timing convergence of one of a digital integrated circuit and functional unit of a digital integrated circuit comprising of the steps of: 
 partitioning the design into macros;    apportioning a timing and area budget to each of said macros;    creating an objective function fo rthe optimization of at least one of said macros having contributions from a plurality of primary output signals in said macro;    improving the timing chracteristics of each of the at least one selected macros by attempting to minimize said objective function;    timing the overall design; and    re-apportioning the timing and area budgets and repeating the said improving and timing steps until the required specifications are met.    
   
   
       2 . The method of  claim 1  wherein said optimization step is achieved using formal optimization techniques.  
   
   
       3 . The method of  claim 1  wherein said optimization step is achieved using heuristic optimization techniques.  
   
   
       4 . The method of  claim 1  wherein said optimization step is achieved using unconstrained optimization techniques.  
   
   
       5 . The method of  claim 1  wherein said optimization step is achieved using constrained optimization techniques.  
   
   
       6 . The method of  claim 1  in which the objective function comprises a summation of penalty contributions from each primary output signal, each of said penalty contributions being a non-decreasing penalty function of the amount by which a timing requirement is violated.  
   
   
       7 . The method of  claim 1  in which the optimiation of the individual macros is carried out in a sequential fashion.  
   
   
       8 . The method of  claim 1  in which the optimization of individual macros is carried out in parallel.  
   
   
       9 . The method of  claim 1  in which the optimization is of one or more of: transistor sizing, buffer insertion, logic optimization, logic restructuring and assignment of multiple threshold voltage devices.  
   
   
       10 . The method of  claim 2  in which the optimization is performed by one or more of: continuous nonlinear optimization, linear programming, branch-and-bound optimization, discrete optimization, dynamic programming, simulated annealing and mixed discrete/continuous optimization.  
   
   
       11 . The method of  claim 1  wherein the underlying design is a combinational circuit.  
   
   
       12 . The method of  claim 1  wherein the underlying desing is a sequential circuit containing one or more of: master slave latches, transparent latches, flip-flops and multiple clocks.  
   
   
       13 . A method of achieving timing convergence of one of a digital integrated circuit and functional unit of a digital integrated circuit comprising the steps of: 
 partitioning the design into macros;    apportioning a macro budget for timing and area to each of said macros;    creating a reformatted objective function for the optimization of at least one of said macros having contributions from a plurality of primary output signals in said macro for improving sub-critical paths and critical paths;    improving the timing characteristics of each of the at least one selected macros by attempting to minimize said objection function;    timing the overall design; and    re-apportioning the timing and area budgets and repeating the said improving and timing steps until the required specifications are met and the sub-critical paths and critical paths are improved.