Inventor · disambiguated record
Peter Thomas Freiburger
Also filed as: FREIBURGER PETER T · FREIBURGER PETER THOMAS
27 granted patents·5 pending applications·309 citations·filing 1998–2019
96Inventor score
Top patents by PatentIndex Score
32 records- 0193US6538522B1Method and ring oscillator for evaluating dynamic circuitsIBM·Filed 2001·Granted Mar 25, 2003·53 cites·20 claims
- 0289US6657886B1Split local and continuous bitline for fast domino read SRAMIBM·Filed 2002·Granted Dec 2, 2003·52 cites·11 claims
- 0379US10381098B2Memory interface latch with integrated write-through and fence functionsIBM·Filed 2017·Granted Aug 13, 2019·2 cites·18 claims
- 0478US10229748B1Memory interface latch with integrated write-through functionIBM·Filed 2017·Granted Mar 12, 2019·4 cites·18 claims
- 0575US6901003B2Lower power and reduced device split local and continuous bitline for domino read SRAMsIBM·Filed 2003·Granted May 31, 2005·21 cites·20 claims
- 0673US7724586B2Implementing local evaluation of domino read SRAM with enhanced SRAM cell stability with minimized area usageIBM·Filed 2008·Granted May 25, 2010·8 cites·18 claims
- 0773US7684263B2Method and circuit for implementing enhanced SRAM write and read performance ring oscillatorIBM·Filed 2008·Granted Mar 23, 2010·8 cites·16 claims
- 0873US6172531B1Low power wordline decoder circuit with minimized hold timeIBM·Filed 1999·Granted Jan 9, 2001·33 cites·19 claims
- 0972US9058866B2SRAM local evaluation logic for column selectionFREIBURGER PETER T·Filed 2012·Granted Jun 16, 2015·5 cites·4 claims
- 1072US7161390B2Dynamic latching logic structure with static interfaces for implementing improved data setup timeIBM·Filed 2004·Granted Jan 9, 2007·15 cites·13 claims
- 1172US5991224AGlobal wire management apparatus and method for a multiple-port random access memoryIBM·Filed 1998·Granted Nov 23, 1999·33 cites·37 claims
- 1267US6741493B1Split local and continuous bitline requiring fewer wiresIBM·Filed 2002·Granted May 25, 2004·15 cites·26 claims
- 1366US7035127B1Method and sum addressed cell encoder for enhanced compare and search timing for CAM compareIBM·Filed 2004·Granted Apr 25, 2006·14 cites·16 claims
- 1463US7443744B2Method for reducing wiring and required number of redundant elementsIBM·Filed 2006·Granted Oct 28, 2008·4 cites·4 claims
- 1562US8427894B2Implementing single bit redundancy for dynamic SRAM circuit with any bit decodeBEHRENDS DERICK G·Filed 2010·Granted Apr 23, 2013·3 cites·20 claims
- 1660US7835176B2Implementing enhanced dual mode SRAM performance screen ring oscillatorIBM·Filed 2009·Granted Nov 16, 2010·4 cites·20 claims
- 1758US9087563B2SRAM local evaluation and write logic for column selectionFREIBURGER PETER T·Filed 2012·Granted Jul 21, 2015·2 cites·4 claims
- 1857US7925950B2Implementing enhanced array access time tracking with logic built in self test of dynamic memory and random logicIBM·Filed 2009·Granted Apr 12, 2011·3 cites·20 claims
- 1954US7681095B2Methods and apparatus for testing integrated circuitsIBM·Filed 2008·Granted Mar 16, 2010·2 cites·9 claims
- 2051US8488368B2Method for selectable guaranteed write-through with early read suppressionCHRISTENSEN TODD A·Filed 2011·Granted Jul 16, 2013·1 cites·17 claims
- 2149US10916323B2Memory interface latch with integrated write-through and fence functionsIBM·Filed 2019·Granted Feb 9, 2021·0 cites·18 claims
- 2249US5991208AWrite multiplexer apparatus and method for multiple write port programmable memoryIBM·Filed 1998·Granted Nov 23, 1999·12 cites·20 claims
- 2343US6272654B1Fast scannable output latch with domino logic inputIBM·Filed 1999·Granted Aug 7, 2001·9 cites·12 claims
- 2440US8107309B2Bias temperature instability-influenced storage cellDEWANZ DOUGLAS M·Filed 2009·Granted Jan 31, 2012·1 cites·12 claims
- 2540US7015600B2Pulse generator circuit and semiconductor device including sameIBM·Filed 2002·Granted Mar 21, 2006·1 cites·16 claims
- 2640US2008273406A1Enhanced sram redundancy circuit for reducing wiring and required number of redundant elementsIBM·Filed 2008·Application pending·0 cites
- 2736US2008112219A1Method and Enhanced SRAM Redundancy Circuit for Reducing Wiring and Required Number of Redundant ElementsIBM·Filed 2007·Application pending·0 cites
- 2834US7418637B2Methods and apparatus for testing integrated circuitsIBM·Filed 2003·Granted Aug 26, 2008·0 cites·12 claims
- 2933US2007047282A1Method and apparatus for implementing power saving for content addressable memoryIBM·Filed 2005·Application pending·0 cites
- 3032US6247166B1Method and apparatus for assembling array and datapath macrosIBM·Filed 1998·Granted Jun 12, 2001·4 cites·21 claims
- 3131US2005125615A1Methods and apparatus for writing an LRU bitIBM·Filed 2003·Application pending·0 cites
- 3228US2009122626A1Method and Apparatus for Selectable Guaranteed Write ThroughFREIBURGER PETER T·Filed 2007·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Peter Thomas Freiburger files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →