Enhanced sram redundancy circuit for reducing wiring and required number of redundant elements

Abstract

A method and enhanced Static Random Access Memory (SRAM) redundancy circuit reduce wiring and the required number of redundant elements. A bitline redundancy mechanism allows the swapping of a pair of bitlines for a redundant pair of bit columns. Two of the adjacent bitlines are swapped out at a time, one even and one odd. The swap is accomplished by steering the data around the bad columns and adding redundant columns on the end that are steered in when needed.

1 . A Static Random Access Memory (SRAM) redundancy circuit including interleaved bit columns with a respective even and odd bits, the SRAM redundancy circuit comprising:
 a bitline redundancy mechanism swapping a pair of bitlines for a redundant bitline pair;   said bitline redundancy mechanism swapping two of the adjacent bitlines at a time, one even and one odd by steering the data around at least one bad column and adding two redundant columns.   
   
   
       2 . The SRAM circuit as recited in  claim 1  includes a plurality of redundancy decode circuits. 
   
   
       3 . The SRAM circuit as recited in  claim 2  includes an embedded redundant enable applied to an input of each of said plurality of redundant decode circuits. 
   
   
       4 . The SRAM circuit as recited in  claim 1  includes a multiplexer providing redundancy steering incorporated with bit decode. 
   
   
       5 . The SRAM circuit as recited in  claim 4  includes logic function combining a bit select (BS) and a redundancy steer select (RS<0:1>) to provide a select input to said multiplexer. 
   
   
       6 . The SRAM circuit as recited in  claim 1  includes a SRAM redundancy decode including a plurality of redundancy decode circuits, and an address predecoder generating inputs applied to said plurality of redundancy decode circuits. 
   
   
       7 . The SRAM circuit as recited in  claim 6  includes a redundant enable signal applied to said address predecoder. 
   
   
       8 . The SRAM circuit as recited in  claim 7  wherein said address predecoder provides an embedded redundant enable applied to an input of each of said plurality of redundancy decode circuits. 
   
   
       9 - 12 . (canceled) 
   
   
       13 . A SRAM redundancy circuit comprising:
 a plurality of interleaved SRAM bit columns of respective even and odd bits;   a multiplexer providing redundancy steering incorporated with bit decode; said multiplexer coupled to said interleaved SRAM bit columns;   a bit select (BS) and a redundancy steer select (RS<0:1>) providing a select input to said multiplexer;   a plurality of redundancy decode circuits, and   an address predecoder generating inputs applied to said plurality of redundancy decode circuits.   
   
   
       14 . The SRAM redundancy circuit as recited in  claim 13  wherein said address predecoder applies an embedded redundant enable to an input of each of said redundancy decode circuits. 
   
   
       15 . The SRAM redundancy circuit as recited in  claim 13  wherein said plurality of redundancy decode circuits includes a respective redundancy decode circuit for each said SRAM bit columns. 
   
   
       16 . The SRAM redundancy circuit as recited in  claim 13  includes a redundant enable signal applied to said address predecoder.