Inventor · disambiguated record
Pedja Raspopovic
Also filed as: RASPOPOVIC PEDJA
20 granted patents·1,747 citations·filing 1998–2022
97Inventor score
Technology areasG06F
Top patents by PatentIndex Score
20 records- 0196US6182272B1Metal layer assignmentLSI LOGIC CORP·Filed 1998·Granted Jan 30, 2001·332 cites·32 claims
- 0293US6324674B2Method and apparatus for parallel simultaneous global and detail routingLSI LOGIC CORP·Filed 1998·Granted Nov 27, 2001·206 cites·36 claims
- 0391US6289495B1Method and apparatus for local optimization of the global routingLSI LOGIC CORP·Filed 1998·Granted Sep 11, 2001·166 cites·20 claims
- 0489US6253363B1Net routing using basis element decompositionLSI LOGIC CORP·Filed 1998·Granted Jun 26, 2001·153 cites·24 claims
- 0589US6230306B1Method and apparatus for minimization of process defects while routingLSI LOGIC CORP·Filed 1998·Granted May 8, 2001·148 cites·31 claims
- 0689US6175950B1Method and apparatus for hierarchical global routing descendLSI LOGIC CORP·Filed 1998·Granted Jan 16, 2001·157 cites·19 claims
- 0787US6412102B1Wire routing optimizationLSI LOGIC CORP·Filed 1998·Granted Jun 25, 2002·139 cites·33 claims
- 0887US6247167B1Method and apparatus for parallel Steiner tree routingLSI LOGIC CORP·Filed 1998·Granted Jun 12, 2001·131 cites·82 claims
- 0981US7020589B1Method and apparatus for adaptive timing optimization of an integrated circuit designLSI LOGIC CORP·Filed 2001·Granted Mar 28, 2006·33 cites·28 claims
- 1080US6643832B1Virtual tree-based netlist model and method of delay estimation for an integrated circuit designLSI LOGIC CORP·Filed 2001·Granted Nov 4, 2003·30 cites·15 claims
- 1180US6546539B1Netlist resynthesis program using structure co-factoringLSI LOGIC CORP·Filed 2000·Granted Apr 8, 2003·39 cites·8 claims
- 1280US6154874AMemory-saving method and apparatus for partitioning high fanout netsLSI LOGIC CORP·Filed 1998·Granted Nov 28, 2000·91 cites·28 claims
- 1371US6557144B1Netlist resynthesis program based on physical delay calculationLSI LOGIC CORP·Filed 2000·Granted Apr 29, 2003·16 cites·7 claims
- 1471US6260183B1Method and apparatus for coarse global routingLSI LOGIC CORP·Filed 1998·Granted Jul 10, 2001·58 cites·33 claims
- 1569US8843865B2Data flow analyzerTAI PHILIP H·Filed 2012·Granted Sep 23, 2014·5 cites·21 claims
- 1664US6505336B1Channel router with buffer insertionLSI LOGIC CORP·Filed 2001·Granted Jan 7, 2003·10 cites·18 claims
- 1763US12443785B1Placing hard macros using machine learning predictions trained on different circuit designsSYNOPSYS INC·Filed 2022·Granted Oct 14, 2025·0 cites·20 claims
- 1857US6463572B1IC timing analysis with known false pathsLSI LOGIC CORP·Filed 2001·Granted Oct 8, 2002·5 cites·19 claims
- 1954US6453453B1Process for solving assignment problems in integrated circuit designs with unimodal object penalty functions and linearly ordered set of boxesLSI LOGIC CORP·Filed 2001·Granted Sep 17, 2002·3 cites·20 claims
- 2052US6269469B1Method and apparatus for parallel routing locking mechanismLSI LOGIC CORP·Filed 1998·Granted Jul 31, 2001·25 cites·22 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →