Inventor · disambiguated record
Perumal Ratnam
Also filed as: RATNAM PERUMAL
22 granted patents·3 pending applications·218 citations·filing 1992–2017
95Inventor score
Files withSANDISK 3D LLC7SANDISK TECHNOLOGIES LLC6RATNAM PERUMAL4ALLIANCE SEMICONDUCTOR CORP3ALLIANCE SEMICONDUCTOR2
Top patents by PatentIndex Score
25 records- 0197US9859337B2Three-dimensional memory device with vertical semiconductor bit lines located in recesses and method of making thereofSANDISK TECHNOLOGIES LLC·Filed 2016·Granted Jan 2, 2018·22 cites·28 claims
- 0297US9818801B1Resistive three-dimensional memory device with heterostructure semiconductor local bit line and method of making thereofSANDISK TECHNOLOGIES LLC·Filed 2016·Granted Nov 14, 2017·24 cites·13 claims
- 0395US9685484B1Reversible resistivity memory with crystalline silicon bit lineSANDISK TECHNOLOGIES LLC·Filed 2016·Granted Jun 20, 2017·18 cites·23 claims
- 0495US9455301B2Setting channel voltages of adjustable resistance bit line structures using dummy word linesSANDISK 3D LLC·Filed 2015·Granted Sep 27, 2016·9 cites·18 claims
- 0592US9373396B2Side wall bit line structuresSANDISK 3D LLC·Filed 2015·Granted Jun 21, 2016·6 cites·18 claims
- 0689US10032908B1Multi-gate vertical field effect transistor with channel strips laterally confined by gate dielectric layers, and method of making thereofSANDISK TECHNOLOGIES LLC·Filed 2017·Granted Jul 24, 2018·7 cites·26 claims
- 0788US9484092B2Intrinsic vertical bit line architectureSANDISK 3D LLC·Filed 2015·Granted Nov 1, 2016·4 cites·20 claims
- 0885US9355736B1Vertical memory cells and methods of operationRATNAM PERUMAL·Filed 2014·Granted May 31, 2016·8 cites·20 claims
- 0984US8885407B1Vertical memory cells and methods, architectures and devices for the sameRATNAM PERUMAL·Filed 2011·Granted Nov 11, 2014·9 cites·8 claims
- 1082US9236122B2Shared-gate vertical-TFT for vertical bit line arraySANDISK 3D LLC·Filed 2014·Granted Jan 12, 2016·6 cites·28 claims
- 1182US7956432B2Photodiode for multiple wavelength operationINTERSIL INC·Filed 2009·Granted Jun 7, 2011·5 cites·18 claims
- 1277US6236608B1Technique to improve the source leakage of flash EPROM cells during source eraseALLIANCE SEMICONDUCTOR·Filed 1999·Granted May 22, 2001·38 cites·28 claims
- 1373US9269425B2Low forming voltage non-volatile storage deviceSANDISK 3D LLC·Filed 2012·Granted Feb 23, 2016·4 cites·19 claims
- 1470US9484093B2Controlling adjustable resistance bit lines connected to word line combsSANDISK 3D LLC·Filed 2015·Granted Nov 1, 2016·1 cites·20 claims
- 1567US6166409AFlash EPROM memory cell having increased capacitive couplingALLIANCE SEMICONDUCTOR CORP·Filed 1996·Granted Dec 26, 2000·23 cites·22 claims
- 1664US6429076B2Flash EPROM memory cell having increased capacitive coupling and method of manufacture thereofALLIANCE SEMICONDUCTOR CORP·Filed 2001·Granted Aug 6, 2002·10 cites·22 claims
- 1762US9922709B2Memory hole bit line structuresSANDISK TECHNOLOGIES LLC·Filed 2015·Granted Mar 20, 2018·1 cites·16 claims
- 1858US6303959B1Semiconductor device having reduced source leakage during source eraseALLIANCE SEMICONDUCTOR CORP·Filed 1999·Granted Oct 16, 2001·17 cites·17 claims
- 1957US9576660B2Low forming voltage non-volatile storage deviceSANDISK 3D LLC·Filed 2016·Granted Feb 21, 2017·1 cites·7 claims
- 2048US2006214251A1Photodiodes with anti-reflection coatingINTERSIL INC·Filed 2006·Application pending·0 cites
- 2145US2013011985A1Shallow-trench cmos-compatible super junction device structure for low and medium voltage power management applicationsRATNAM PERUMAL·Filed 2012·Application pending·0 cites
- 2243US2012273882A1Shallow-trench cmos-compatible super junction device structure for low and medium voltage power management applicationsRATNAM PERUMAL·Filed 2011·Application pending·0 cites
- 2338US10388870B2Barrier modulated cell structures with intrinsic vertical bit line architectureSANDISK TECHNOLOGIES LLC·Filed 2017·Granted Aug 20, 2019·0 cites·10 claims
- 2433US5338695AMaking walled emitter bipolar transistor with reduced base narrowingNAT SEMICONDUCTOR CORP·Filed 1992·Granted Aug 16, 1994·5 cites·12 claims
- 2531US6456537B1Techniques for erasing an erasable programmable read only memory (EPROM) cellALLIANCE SEMICONDUCTOR·Filed 2001·Granted Sep 24, 2002·0 cites·15 claims
Join the waitlist — get patent alerts
Get an alert when Perumal Ratnam files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →