Inventor · disambiguated record
Phong T. Tran
Also filed as: TRAN PHONG T · TRAN PHONG THIEU
21 granted patents·2 pending applications·174 citations·filing 2003–2023
94Inventor score
Top patents by PatentIndex Score
23 records- 0194US9552449B1Dynamic fault model generation for diagnostics simulation and pattern generationIBM·Filed 2016·Granted Jan 24, 2017·6 cites·18 claims
- 0292US6961886B2Diagnostic method for structural scan chain designsIBM·Filed 2003·Granted Nov 1, 2005·59 cites·19 claims
- 0390US7908532B2Automated system and processing for expedient diagnosis of broken shift registers latch chainsIBM·Filed 2008·Granted Mar 15, 2011·22 cites·20 claims
- 0489US9852245B2Dynamic fault model generation for diagnostics simulation and pattern generationIBM·Filed 2017·Granted Dec 26, 2017·3 cites·20 claims
- 0587US10024910B2Iterative N-detect based logic diagnostic techniqueIBM·Filed 2016·Granted Jul 17, 2018·3 cites·20 claims
- 0682US8086924B2Implementing diagnosis of transitional scan chain defects using logic built in self test LBIST test patternsFORLENZA DONATO ORAZIO·Filed 2008·Granted Dec 27, 2011·13 cites·20 claims
- 0782US7934134B2Method and apparatus for performing logic built-in self-testing of an integrated circuitIBM·Filed 2008·Granted Apr 26, 2011·11 cites·15 claims
- 0879US7908534B2Diagnosable general purpose test registers scan chain designIBM·Filed 2008·Granted Mar 15, 2011·9 cites·6 claims
- 0978US7930601B2AC ABIST diagnostic method, apparatus and program productIBM·Filed 2008·Granted Apr 19, 2011·11 cites·16 claims
- 1077US7392449B2Method, apparatus, and computer program product for diagnosing a scan chain failure employing fuses coupled to the scan chainIBM·Filed 2007·Granted Jun 24, 2008·7 cites·11 claims
- 1172US7921346B2Verification of array built-in self-test (ABIST) design-for-test/design-for-diagnostics (DFT/DFD)IBM·Filed 2008·Granted Apr 5, 2011·6 cites·1 claims
- 1271US7831863B2Method for enhancing the diagnostic accuracy of a VLSI chipIBM·Filed 2007·Granted Nov 9, 2010·5 cites·18 claims
- 1370US7395470B2Method, apparatus, and computer program product for diagnosing a scan chain failure employing fuses coupled to the scan chainIBM·Filed 2005·Granted Jul 1, 2008·4 cites·9 claims
- 1467US7395469B2Method for implementing deterministic based broken scan chain diagnosticsIBM·Filed 2004·Granted Jul 1, 2008·12 cites·11 claims
- 1565US10768230B2Built-in device testing of integrated circuitsIBM·Filed 2016·Granted Sep 8, 2020·1 cites·17 claims
- 1663US10254336B2Iterative N-detect based logic diagnostic techniqueIBM·Filed 2018·Granted Apr 9, 2019·0 cites·20 claims
- 1760US10169510B2Dynamic fault model generation for diagnostics simulation and pattern generationIBM·Filed 2017·Granted Jan 1, 2019·0 cites·20 claims
- 1859US11940271B2High power device fault localization via die surface contouringIBM·Filed 2020·Granted Mar 26, 2024·0 cites·20 claims
- 1956US12393543B2System and method for utilizing a data storage device with power performance profiles and/or temperature monitoringWESTERN DIGITAL TECH INC·Filed 2023·Granted Aug 19, 2025·0 cites·21 claims
- 2056US7475308B2implementing deterministic based broken scan chain diagnosticsIBM·Filed 2008·Granted Jan 6, 2009·2 cites·7 claims
- 2139US8065575B2Implementing isolation of VLSI scan chain using ABIST test patternsFORLENZA DONATO ORAZIO·Filed 2008·Granted Nov 22, 2011·0 cites·20 claims
- 2239US2009210761A1AC Scan Diagnostic Method and Apparatus Utilizing Functional Architecture Verification PatternsFORLENZA DONATO O·Filed 2008·Application pending·0 cites
- 2338US2008115029A1iterative test generation and diagnostic method based on modeled and unmodeled faultsIBM·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →