Inventor · disambiguated record
Pinhong Chen
Also filed as: CHEN PINHONG
13 granted patents·379 citations·filing 2002–2021
93Inventor score
Top patents by PatentIndex Score
13 records- 0196US6971076B2Method for estimating peak crosstalk noise based on separate crosstalk modelCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Nov 29, 2005·192 cites·15 claims
- 0294US7739629B2Method and mechanism for implementing electronic designs having power information specifications backgroundCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jun 15, 2010·42 cites·29 claims
- 0391US7954078B1High level IC design with power specification and power source hierarchyCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted May 31, 2011·35 cites·16 claims
- 0489US9026978B1Reverse interface logic model for optimizing physical hierarchy under full chip constraintCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted May 5, 2015·32 cites·20 claims
- 0589US8516422B1Method and mechanism for implementing electronic designs having power information specifications backgroundWANG QI·Filed 2010·Granted Aug 20, 2013·13 cites·31 claims
- 0689US7551985B1Method and apparatus for power consumption optimization for integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jun 23, 2009·31 cites·21 claims
- 0788US11775723B1Methods, systems, and computer program products for efficiently implementing a 3D-ICCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Oct 3, 2023·4 cites·20 claims
- 0887US11276677B1Concurrent optimization of 3D-IC with asymmetrical routing layersCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Mar 15, 2022·3 cites·21 claims
- 0980USRE44479EMethod and mechanism for implementing electronic designs having power information specifications backgroundWANG QI·Filed 2012·Granted Sep 3, 2013·5 cites·29 claims
- 1078US10204180B1Method, system, and computer program product for implementing electronic designs with automatically generated power intentCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Feb 12, 2019·4 cites·25 claims
- 1177US10706199B1Graphical user interface for interactive macro-cell placementCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Jul 7, 2020·4 cites·20 claims
- 1274US9652582B1Multi-instantiated block timing optimizationCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted May 16, 2017·2 cites·20 claims
- 1365US7082587B2Method of estimating path delays in an ICCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Jul 25, 2006·12 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →