Inventor · disambiguated record
Prakash Gopalakrishnan
Also filed as: GOPALAKRISHNAN PRAKASH
11 granted patents·126 citations·filing 2002–2012
91Inventor score
Technology areasG06F
Top patents by PatentIndex Score
11 records- 0192US8261228B1Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracyGOPALAKRISHNAN PRAKASH·Filed 2008·Granted Sep 4, 2012·42 cites·14 claims
- 0290US9330222B2Methods, systems, and articles of manufacture for implementing electronic circuit designs with electro-migration awarenessWHITE DAVID·Filed 2010·Granted May 3, 2016·12 cites·51 claims
- 0388US7665054B1Optimizing circuit layouts by configuring rooms for placing devicesCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Feb 16, 2010·27 cites·36 claims
- 0485US8584072B1Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracyGOPALAKRISHNAN PRAKASH·Filed 2012·Granted Nov 12, 2013·9 cites·17 claims
- 0583US8694933B2Methods, systems, and articles of manufacture for implementing electronic circuit designs with simulation awarenessGOPALAKRISHNAN PRAKASH·Filed 2010·Granted Apr 8, 2014·5 cites·54 claims
- 0681US8612921B1Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracyGOPALAKRISHNAN PRAKASH·Filed 2012·Granted Dec 17, 2013·6 cites·8 claims
- 0779US8694950B2Methods, systems, and articles of manufacture for implementing electronic circuit designs with electrical awarenessMCSHERRY MICHAEL·Filed 2010·Granted Apr 8, 2014·4 cites·35 claims
- 0868US7533358B2Integrated sizing, layout, and extractor tool for circuit designCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted May 12, 2009·4 cites·21 claims
- 0968US6874133B2Integrated circuit design layout compaction methodCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Mar 29, 2005·14 cites·13 claims
- 1060US8527928B1Optimizing circuit layouts by configuring rooms for placing devicesGOPALAKRISHNAN PRAKASH·Filed 2009·Granted Sep 3, 2013·2 cites·20 claims
- 1155US7584440B2Method and system for tuning a circuitCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Sep 1, 2009·1 cites·27 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →