Inventor · disambiguated record
Promod Kumar
Also filed as: KUMAR PROMOD
34 granted patents·11 pending applications·412 citations·filing 1996–2025
97Inventor score
Files withST MICROELECTRONICS INT NV26ST MICROELECTRONICS SRL12CHAWLA NITIN2ST MICROELECTRONICS PVT LTD1STMICROELECTONICS S R L1
Top patents by PatentIndex Score
45 records- 0192US6587913B2Interleaved memory device for burst type access in synchronous read mode with the two semi-arrays independently readable in random access asynchronous modeST MICROELECTRONICS SRL·Filed 2001·Granted Jul 1, 2003·85 cites·53 claims
- 0291US6470431B2Interleaved data path and output management architecture for an interleaved memory and load pulser circuit for outputting the read dataST MICROELECTRONICS SRL·Filed 2001·Granted Oct 22, 2002·71 cites·34 claims
- 0389US11984151B2Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2022·Granted May 14, 2024·3 cites·32 claims
- 0488US12087356B2Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2022·Granted Sep 10, 2024·2 cites·33 claims
- 0587US8218377B2Fail-safe high speed level shifter for wide supply voltage rangeTANDON AMIT·Filed 2009·Granted Jul 10, 2012·24 cites·25 claims
- 0687US6624679B2Stabilized delay circuitST MICROELECTRONICS SRL·Filed 2001·Granted Sep 23, 2003·49 cites·26 claims
- 0783US8154335B2Fail safe adaptive voltage/frequency systemCHAWLA NITIN·Filed 2009·Granted Apr 10, 2012·13 cites·22 claims
- 0881US6473339B2Redundancy architecture for an interleaved memoryST MICROELECTRONICS SRL·Filed 2001·Granted Oct 29, 2002·32 cites·26 claims
- 0978US8269545B2Fail safe adaptive voltage/frequency systemCHAWLA NITIN·Filed 2011·Granted Sep 18, 2012·5 cites·20 claims
- 1076US7050343B2Built-in testing methodology in flash memoryST MICROELECTRONICS SRL·Filed 2004·Granted May 23, 2006·30 cites·11 claims
- 1176US6452864B1Interleaved memory device for sequential access synchronous reading with simplified address countersSTMICROELECTONICS S R L·Filed 2001·Granted Sep 17, 2002·30 cites·9 claims
- 1276US2025308574A1Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)ST MICROELECTRONICS INT NV·Filed 2025·Application pending·0 cites
- 1374US6282134B1Memory test method and nonvolatile memory with low error masking probabilityST MICROELECTRONICS SRL·Filed 2000·Granted Aug 28, 2001·24 cites·15 claims
- 1468US6438048B1Nonvolatile memory and high speed memory test methodST MICROELECTRONICS SRL·Filed 2000·Granted Aug 20, 2002·18 cites·27 claims
- 1568US2025078883A1Bit-cell architecture based in-memory computeST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 1668US2025054529A1Sram with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applicationsST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 1767US7750689B1High voltage switch with reduced voltage stress at output stageST MICROELECTRONICS PVT LTD·Filed 2008·Granted Jul 6, 2010·5 cites·8 claims
- 1867US2025174269A1Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)ST MICROELECTRONICS INT NV·Filed 2025·Application pending·0 cites
- 1966US2024395319A1Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)ST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 2066US2025069678A1Built-in self test circuit for segmented static random access memory (sram) array input/outputST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 2165US12183424B2Bit-cell architecture based in-memory computeST MICROELECTRONICS INT NV·Filed 2022·Granted Dec 31, 2024·0 cites·33 claims
- 2265US11726543B2Computing system power management device, system and methodST MICROELECTRONICS SRL·Filed 2020·Granted Aug 15, 2023·0 cites·19 claims
- 2364US12292780B2Computing system power management device, system and methodST MICROELECTRONICS SRL·Filed 2023·Granted May 6, 2025·0 cites·14 claims
- 2463US12437825B2At-speed transition fault testing for a multi-port and multi-clock memoryST MICROELECTRONICS INT NV·Filed 2023·Granted Oct 7, 2025·0 cites·40 claims
- 2562US12482518B2Enhanced accuracy of bit line reading for an in-memory compute operation by accounting for variation in read currentST MICROELECTRONICS INT NV·Filed 2023·Granted Nov 25, 2025·0 cites·12 claims
- 2662US12469545B2Bit line read current mirroring circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2023·Granted Nov 11, 2025·0 cites·42 claims
- 2762US12170120B2Built-in self test circuit for segmented static random access memory (SRAM) array input/outputST MICROELECTRONICS INT NV·Filed 2023·Granted Dec 17, 2024·0 cites·38 claims
- 2862US12159689B2SRAM with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applicationsST MICROELECTRONICS INT NV·Filed 2022·Granted Dec 3, 2024·0 cites·19 claims
- 2961US12328858B2Silicon-on-insulator semiconductor device with a static random access memory circuitSTMICROELECTRONICS FRANCE·Filed 2023·Granted Jun 10, 2025·0 cites·22 claims
- 3060US12237007B2Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2022·Granted Feb 25, 2025·0 cites·39 claims
- 3159US12354644B2Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2022·Granted Jul 8, 2025·0 cites·30 claims
- 3257US6487140B2Circuit for managing the transfer of data streams from a plurality of sources within a systemST MICROELECTRONICS SRL·Filed 2001·Granted Nov 26, 2002·10 cites·39 claims
- 3356US12353341B2Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selectionST MICROELECTRONICS INT NV·Filed 2023·Granted Jul 8, 2025·0 cites·19 claims
- 3454US12406705B2In-memory computation circuit using static random access memory (SRAM) array segmentationST MICROELECTRONICS INT NV·Filed 2023·Granted Sep 2, 2025·0 cites·24 claims
- 3551US2025054528A1Sram with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applicationsST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 3648US12361982B2Memory architecture supporting both conventional memory access mode and digital in-memory computation processing modeST MICROELECTRONICS INT NV·Filed 2023·Granted Jul 15, 2025·0 cites·19 claims
- 3746US2024177769A1Bit line accumulation readout scheme for an analog in-memory computation processing circuitST MICROELECTRONICS INT NV·Filed 2023·Application pending·0 cites
- 3844US2023386565A1In-memory computation circuit using static random access memory (sram) array segmentation and local compute tile read based on weighted currentST MICROELECTRONICS INT NV·Filed 2023·Application pending·0 cites
- 3944US2024112728A1Analog in-memory computation processing circuit using segmented memory architectureST MICROELECTRONICS INT NV·Filed 2023·Application pending·0 cites
- 4044US2023386566A1Bit line voltage clamping read circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)ST MICROELECTRONICS INT NV·Filed 2023·Application pending·0 cites
- 4143US12046324B2Modular memory architecture with gated sub-array operation dependent on stored data contentST MICROELECTRONICS INT NV·Filed 2022·Granted Jul 23, 2024·0 cites·38 claims
- 4242US12176025B2Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2022·Granted Dec 24, 2024·0 cites·51 claims
- 4342US6625706B2ATD generation in a synchronous memoryST MICROELECTRONICS SRL·Filed 2001·Granted Sep 23, 2003·3 cites·26 claims
- 4438US6638818B1Method of fabricating a dynamic random access memory with increased capacitanceTEXAS INSTRUMENTS INC·Filed 1996·Granted Oct 28, 2003·6 cites·20 claims
- 4537US6366634B2Accelerated carry generationST MICROELECTRONICS SRL·Filed 2001·Granted Apr 2, 2002·2 cites·21 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →