Inventor · disambiguated record
Qingyun Yang
Also filed as: YANG QINGYUN
15 granted patents·4 pending applications·683 citations·filing 2001–2024
93Inventor score
Top patents by PatentIndex Score
19 records- 0198US6864041B2Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etchingIBM·Filed 2001·Granted Mar 8, 2005·538 cites·12 claims
- 0288US7816275B1Gate patterning of nano-channel devicesIBM·Filed 2009·Granted Oct 19, 2010·13 cites·18 claims
- 0384US11258012B2Oxygen-free plasma etching for contact etching of resistive random access memoryTOKYO ELECTRON LTD·Filed 2019·Granted Feb 22, 2022·5 cites·20 claims
- 0484US8481389B2Method of removing high-K dielectric layer on sidewalls of gate structureZHANG YING·Filed 2011·Granted Jul 9, 2013·7 cites·16 claims
- 0583US11844290B2Plasma co-doping to reduce the forming voltage in resistive random access memory (ReRAM) devicesTOKYO ELECTRON LTD·Filed 2021·Granted Dec 12, 2023·1 cites·21 claims
- 0683US7435652B1Integration schemes for fabricating polysilicon gate MOSFET and high-K dielectric metal gate MOSFETIBM·Filed 2007·Granted Oct 14, 2008·11 cites·20 claims
- 0783US6541320B2Method to controllably form notched polysilicon gate structuresIBM·Filed 2001·Granted Apr 1, 2003·32 cites·24 claims
- 0876US8445948B2Gate patterning of nano-channel devicesFULLER NICHOLAS C M·Filed 2010·Granted May 21, 2013·4 cites·14 claims
- 0976US6960510B2Method of making sub-lithographic featuresIBM·Filed 2002·Granted Nov 1, 2005·21 cites·11 claims
- 1075US9105741B2Method of replacement source/drain for 3D CMOS transistorsCHAN KEVIN K·Filed 2012·Granted Aug 11, 2015·4 cites·13 claims
- 1171US6828187B1Method for uniform reactive ion etching of dual pre-doped polysilicon regionsIBM·Filed 2004·Granted Dec 7, 2004·17 cites·20 claims
- 1271US6509219B2Fabrication of notched gates by passivating partially etched gate sidewalls and then using an isotropic etchIBM·Filed 2001·Granted Jan 21, 2003·17 cites·32 claims
- 1364US6703269B2Method to form gate conductor structures of dual doped polysiliconIBM·Filed 2002·Granted Mar 9, 2004·13 cites·20 claims
- 1457US2025279281A1Halogen gas mixtures for through-substrate etchingTOKYO ELECTRON LTD·Filed 2024·Application pending·0 cites
- 1552US2023329127A1Resistive memory device and method of formingTOKYO ELECTRON LTD·Filed 2023·Application pending·0 cites
- 1649US12057322B2Methods for etching metal films using plasma processingTOKYO ELECTRON LTD·Filed 2019·Granted Aug 6, 2024·0 cites·12 claims
- 1746US10651372B2Process for patterning a magnetic tunnel junctionTOKYO ELECTRON LTD·Filed 2018·Granted May 12, 2020·0 cites·19 claims
- 1844US2008194112A1Method and system for plasma etching having improved across-wafer etch uniformityIBM·Filed 2007·Application pending·0 cites
- 1940US2008182372A1Method of forming disposable spacers for improved stressed nitride film effectivenessIBM·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →