Inventor · disambiguated record
Rammohan Narayan
Also filed as: NARAYAN RAMMOHAN
26 granted patents·626 citations·filing 1995–1999
97Inventor score
Technology areasG06F
Files withADVANCED MICRO DEVICES INC26
Top patents by PatentIndex Score
26 records- 0181US5822559AApparatus and method for aligning variable byte-length instructions to a plurality of issue positionsADVANCED MICRO DEVICES INC·Filed 1996·Granted Oct 13, 1998·100 cites·25 claims
- 0279US5748978AByte queue divided into multiple subqueues for optimizing instruction selection logicADVANCED MICRO DEVICES INC·Filed 1996·Granted May 5, 1998·92 cites·20 claims
- 0368US5850532AInvalid instruction scan unit for detecting invalid predecode data corresponding to instructions being fetchedADVANCED MICRO DEVICES INC·Filed 1997·Granted Dec 15, 1998·55 cites·15 claims
- 0467US6085311AInstruction alignment unit employing dual instruction queues for high frequency instruction dispatchADVANCED MICRO DEVICES INC·Filed 1999·Granted Jul 4, 2000·38 cites·25 claims
- 0558US6049863APredecoding technique for indicating locations of opcode bytes in variable byte-length instructions within a superscalar microprocessorADVANCED MICRO DEVICES INC·Filed 1997·Granted Apr 11, 2000·28 cites·18 claims
- 0658US5781789ASuperscaler microprocessor employing a parallel mask decoderADVANCED MICRO DEVICES INC·Filed 1995·Granted Jul 14, 1998·34 cites·18 claims
- 0754US6076146ACache holding register for delayed update of a cache line into an instruction cacheADVANCED MICRO DEVICES INC·Filed 1999·Granted Jun 13, 2000·25 cites·19 claims
- 0853US5983321ACache holding register for receiving instruction packets and for providing the instruction packets to a predecode unit and instruction cacheADVANCED MICRO DEVICES INC·Filed 1997·Granted Nov 9, 1999·25 cites·19 claims
- 0953US5872947AInstruction classification circuit configured to classify instructions into a plurality of instruction types prior to decoding said instructionsADVANCED MICRO DEVICES INC·Filed 1995·Granted Feb 16, 1999·26 cites·21 claims
- 1052US5859991AParallel and scalable method for identifying valid instructions and a superscalar microprocessor including an instruction scanning unit employing the methodADVANCED MICRO DEVICES INC·Filed 1997·Granted Jan 12, 1999·25 cites·42 claims
- 1149US5935239AParallel mask decoder and method for generating said maskADVANCED MICRO DEVICES INC·Filed 1998·Granted Aug 10, 1999·18 cites·13 claims
- 1249US5875315AParallel and scalable instruction scanning unitADVANCED MICRO DEVICES INC·Filed 1997·Granted Feb 23, 1999·22 cites·22 claims
- 1349US5872946AInstruction alignment unit employing dual instruction queues for high frequency instruction dispatchADVANCED MICRO DEVICES INC·Filed 1997·Granted Feb 16, 1999·16 cites·21 claims
- 1448US5968163AMicrocode scan unit for scanning microcode instructions using predecode dataADVANCED MICRO DEVICES INC·Filed 1997·Granted Oct 19, 1999·18 cites·10 claims
- 1548US5826071AParallel mask decoder and method for generating said maskADVANCED MICRO DEVICES INC·Filed 1995·Granted Oct 20, 1998·17 cites·6 claims
- 1646US5852727AInstruction scanning unit for locating instructions via parallel scanning of start and end byte informationADVANCED MICRO DEVICES INC·Filed 1997·Granted Dec 22, 1998·18 cites·20 claims
- 1745US5884058AMethod for concurrently dispatching microcode and directly-decoded instructions in a microprocessorADVANCED MICRO DEVICES INC·Filed 1997·Granted Mar 16, 1999·13 cites·22 claims
- 1842US5859992AInstruction alignment using a dispatch list and a latch listADVANCED MICRO DEVICES INC·Filed 1997·Granted Jan 12, 1999·19 cites·19 claims
- 1938US5940602AMethod and apparatus for predecoding variable byte length instructions for scanning of a number of RISC operationsADVANCED MICRO DEVICES INC·Filed 1997·Granted Aug 17, 1999·9 cites·18 claims
- 2037US6202142B1Microcode scan unit for scanning microcode instructions using predecode dataADVANCED MICRO DEVICES INC·Filed 1999·Granted Mar 13, 2001·9 cites·19 claims
- 2136US6161172AMethod for concurrently dispatching microcode and directly-decoded instructions in a microprocessorADVANCED MICRO DEVICES INC·Filed 1998·Granted Dec 12, 2000·6 cites·19 claims
- 2233US5898851AMethod and apparatus for five bit predecoding variable length instructions for scanning of a number of RISC operationsADVANCED MICRO DEVICES INC·Filed 1997·Granted Apr 27, 1999·5 cites·11 claims
- 2331US5951675AInstruction alignment unit employing dual instruction queues for high frequency instruction dispatchADVANCED MICRO DEVICES INC·Filed 1998·Granted Sep 14, 1999·2 cites·24 claims
- 2431US5867680AMicroprocessor configured to simultaneously dispatch microcode and directly-decoded instructionsADVANCED MICRO DEVICES INC·Filed 1996·Granted Feb 2, 1999·2 cites·18 claims
- 2530US6148393AApparatus for generating a valid maskADVANCED MICRO DEVICES INC·Filed 1998·Granted Nov 14, 2000·2 cites·19 claims
- 2630US5900013ADual comparator scheme for detecting a wrap-around condition and generating a cancel signal for removing wrap-around buffer entriesADVANCED MICRO DEVICES INC·Filed 1996·Granted May 4, 1999·2 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →