Inventor · disambiguated record
Rahul Razdan
Also filed as: RAZDAN RAHUL
27 granted patents·3 pending applications·992 citations·filing 1993–2018
97Inventor score
Files withCOMPAQ INFORMATION TECHNOLOGIE7DIGITAL EQUIPMENT CORP7COMPAQ COMPUTER CORP6MICROSOFT TECHNOLOGY LICENSING LLC3CADENCE DESIGN SYSTEMS INC2
Top patents by PatentIndex Score
30 records- 0194US6249846B1Distributed data dependency stall mechanismCOMPAQ COMPUTER CORP·Filed 2000·Granted Jun 19, 2001·92 cites·8 claims
- 0284US6714902B1Method and apparatus for critical and false path verificationCADENCE DESIGN SYSTEMS INC·Filed 2000·Granted Mar 30, 2004·54 cites·22 claims
- 0383US6463523B1Method and apparatus for delaying the execution of dependent loadsCOMPAQ INFORMATION TECHNOLOGIE·Filed 1999·Granted Oct 8, 2002·101 cites·46 claims
- 0483US5819064AHardware extraction technique for programmable reduced instruction set computersHARVARD COLLEGE·Filed 1995·Granted Oct 6, 1998·106 cites·16 claims
- 0579US6085294ADistributed data dependency stall mechanismCOMPAQ COMPUTER CORP·Filed 1997·Granted Jul 4, 2000·75 cites·27 claims
- 0678US5696956ADynamically programmable reduced instruction set computer with programmable processor loading on program number field and program number register contentsDIGITAL EQUIPMENT CORP·Filed 1995·Granted Dec 9, 1997·103 cites·6 claims
- 0770US6035123ADetermining hardware complexity of software operationsDIGITAL EQUIPMENT CORP·Filed 1995·Granted Mar 7, 2000·59 cites·18 claims
- 0868US10747794B2Smart search for annotations and inkingMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2018·Granted Aug 18, 2020·2 cites·17 claims
- 0967US6141734AMethod and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocolCOMPAQ COMPUTER CORP·Filed 1998·Granted Oct 31, 2000·51 cites·15 claims
- 1064US7039887B2Method and apparatus for enhancing the performance of event driven dynamic simulation of digital circuits based on netlist partitioning techniquesCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted May 2, 2006·15 cites·48 claims
- 1164US6199153B1Method and apparatus for minimizing pincount needed by external memory control chip for multiprocessors with limited memory size requirementsDIGITAL EQUIPMENT CORP·Filed 1998·Granted Mar 6, 2001·24 cites·21 claims
- 1263US5550760ASimulation of circuitsDIGITAL EQUIPMENT CORP·Filed 1993·Granted Aug 27, 1996·46 cites·8 claims
- 1359US10630755B2Selective consumption of web page data over a data-limited connectionMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2017·Granted Apr 21, 2020·1 cites·20 claims
- 1459US6397302B1Method and apparatus for developing multiprocessor cache control protocols by presenting a clean victim signal to an external systemCOMPAQ INFORMATION TECHNOLOGIE·Filed 1998·Granted May 28, 2002·34 cites·13 claims
- 1559US6253285B1Method and apparatus for minimizing dcache index match aliasing using hashing in synonym/subset processingCOMPAQ COMPUTER CORP·Filed 1998·Granted Jun 26, 2001·36 cites·23 claims
- 1656US5694579AUsing pre-analysis and a 2-state optimistic model to reduce computation in transistor circuit simulationDIGITAL EQUIPMENT CORP·Filed 1993·Granted Dec 2, 1997·33 cites·3 claims
- 1756US2015095141A1Method, apparatus, and computer program product for facilitating marketing between businessesADVTRAVL INC·Filed 2013·Application pending·0 cites
- 1854US6446143B1Methods and apparatus for minimizing the impact of excessive instruction retrievalCOMPAQ INFORMATION TECHNOLOGIE·Filed 1998·Granted Sep 3, 2002·27 cites·18 claims
- 1952US5463561AHigh capacity netlist comparisonDIGITAL EQUIPMENT CORP·Filed 1993·Granted Oct 31, 1995·24 cites·17 claims
- 2050US5924120AMethod and apparatus for maximizing utilization of an internal processor bus in the context of external transactions running at speeds fractionally greater than internal transaction timesDIGITAL EQUIPMENT CORP·Filed 1998·Granted Jul 13, 1999·23 cites·14 claims
- 2149US6493802B1Method and apparatus for performing speculative memory fills into a microprocessorCOMPAQ INFORMATION TECHNOLOGIE·Filed 1998·Granted Dec 10, 2002·21 cites·21 claims
- 2246US6295583B1Method and apparatus for resolving probes in multi-processor systems which do not use external duplicate tags for probe filteringCOMPAQ INFORMATION TECHNOLOGIE·Filed 1998·Granted Sep 25, 2001·20 cites·9 claims
- 2345US6349366B1Method and apparatus for developing multiprocessor cache control protocols using a memory management system generating atomic probe commands and system data control response commandsCOMPAQ INFORMATION TECHNOLOGIE·Filed 1998·Granted Feb 19, 2002·17 cites·20 claims
- 2440US10102194B2Shared knowledge about contentsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2016·Granted Oct 16, 2018·0 cites·20 claims
- 2537US6314496B1Method and apparatus for developing multiprocessor cache control protocols using atomic probe commands and system data control response commandsCOMPAQ COMPUTER CORP·Filed 1998·Granted Nov 6, 2001·9 cites·27 claims
- 2636US6401173B1Method and apparatus for optimizing bcache tag performance by inferring bcache tag state from internal processor stateCOMPAQ INFORMATION TECHNOLOGIE·Filed 1999·Granted Jun 4, 2002·8 cites·7 claims
- 2734US6253301B1Method and apparatus for a dedicated physically indexed copy of the data cache tag arraysCOMPAQ COMPUTER CORP·Filed 1998·Granted Jun 26, 2001·7 cites·7 claims
- 2833US2013198739A1Validation of Business Continuity Preparedness of a Virtual MachineRAZDAN RAHUL·Filed 2012·Application pending·0 cites
- 2932US6651144B1Method and apparatus for developing multiprocessor cache control protocols using an external acknowledgement signal to set a cache to a dirty stateHEWLETT PACKARD DEVELOPMENT CO·Filed 1998·Granted Nov 18, 2003·4 cites·13 claims
- 3030US2001029574A1Method and apparatus for developing multiprocessore cache control protocols using a memory management system generating an external acknowledgement signal to set a cache to a dirty coherence stateFiled 1998·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →