Inventor · disambiguated record
Raminderpal Singh
Also filed as: SINGH RAMINDERPAL
16 granted patents·2 pending applications·280 citations·filing 2000–2012
94Inventor score
Top patents by PatentIndex Score
18 records- 0192US7000214B2Method for designing an integrated circuit having multiple voltage domainsIBM·Filed 2003·Granted Feb 14, 2006·79 cites·20 claims
- 0288US8285414B2Method and system for evaluating a machine tool operating characteristicsAHARONI EHUD·Filed 2009·Granted Oct 9, 2012·22 cites·27 claims
- 0384US7246055B1Open system for simulation engines to communicate across multiple sites using a portal methodologyCADENCE DESIGN SYSTEMS INC·Filed 2000·Granted Jul 17, 2007·42 cites·44 claims
- 0478US7139990B2Method of checking the layout versus the schematic of multi-fingered MOS transistor layouts using a sub-circuit based extractionIBM·Filed 2004·Granted Nov 21, 2006·29 cites·15 claims
- 0577US7089512B2Method for optimal use of direct fit and interpolated models in schematic custom design of electrical circuitsIBM·Filed 2004·Granted Aug 8, 2006·23 cites·22 claims
- 0675US8594826B2Method and system for evaluating a machine tool operating characteristicsAHARONI EHUD·Filed 2012·Granted Nov 26, 2013·3 cites·25 claims
- 0772US8021941B2Bias-controlled deep trench substrate noise isolation integrated circuit device structuresIBM·Filed 2009·Granted Sep 20, 2011·4 cites·3 claims
- 0870US6825490B1On chip resistor calibration structure and methodIBM·Filed 2003·Granted Nov 30, 2004·14 cites·20 claims
- 0969US8212332B2Bias-controlled deep trench substrate noise isolation integrated circuit device structuresCHAPMAN PHILLIP FRANCIS·Filed 2011·Granted Jul 3, 2012·3 cites·17 claims
- 1069US6950997B2Method and system for low noise integrated circuit designIBM·Filed 2003·Granted Sep 27, 2005·17 cites·24 claims
- 1169US6826025B2Method and apparatus for providing ESD protection and/or noise reduction in an integrated circuitIBM·Filed 2002·Granted Nov 30, 2004·14 cites·5 claims
- 1266US6744112B2Multiple chip guard rings for integrated circuit and chip guard ring interconnectIBM·Filed 2002·Granted Jun 1, 2004·13 cites·20 claims
- 1355US6865725B2Method and system for integrated circuit designIBM·Filed 2003·Granted Mar 8, 2005·6 cites·20 claims
- 1453US7020857B2Method and apparatus for providing noise suppression in a integrated circuitIBM·Filed 2002·Granted Mar 28, 2006·5 cites·21 claims
- 1553US6954920B2Method, program product, and design tool for automatic transmission line selection in application specific integrated circuitsIBM·Filed 2003·Granted Oct 11, 2005·3 cites·20 claims
- 1648US7309898B1Method and apparatus for providing noise suppression in an integrated circuitIBM·Filed 2002·Granted Dec 18, 2007·3 cites·5 claims
- 1746US2009031260A1Method, Computer Program and System Providing for Semiconductor Processes OptimizationANGYAL MATTHEW·Filed 2007·Application pending·0 cites
- 1836US2005062137A1Vertically-stacked co-planar transmission line structure for IC designIBM·Filed 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →