Inventor · disambiguated record
Ranganathan Sudhakar
Also filed as: SUDHAKAR RANGANATHAN
13 granted patents·7 pending applications·27 citations·filing 2007–2015
87Inventor score
Technology areasG06F
Top patents by PatentIndex Score
20 records- 0175US8082425B2Reliable execution using compare and transfer instruction on an SMT machineSUDHAKAR RANGANATHAN·Filed 2009·Granted Dec 20, 2011·8 cites·20 claims
- 0273US9870225B2Processor with virtualized instruction set architecture and methodsIMAGINATION TECH LTD·Filed 2014·Granted Jan 16, 2018·3 cites·22 claims
- 0372US9720840B2Way lookaheadIMAGINATION TECH LLC·Filed 2013·Granted Aug 1, 2017·4 cites·17 claims
- 0470US7836278B2Three operand instruction extension for X86 architectureADVANCED MICRO DEVICES INC·Filed 2007·Granted Nov 16, 2010·6 cites·17 claims
- 0567US9235510B2Processor with kernel mode access to user space virtual addressesMIPS TECH INC·Filed 2012·Granted Jan 12, 2016·3 cites·24 claims
- 0664US10108548B2Processors and methods for cache sparing storesIMAGINATION TECH LTD·Filed 2015·Granted Oct 23, 2018·1 cites·21 claims
- 0752US8909904B2Combined byte-permute and bit shift unitSUDHAKAR RANGANATHAN·Filed 2009·Granted Dec 9, 2014·1 cites·20 claims
- 0852US8539397B2Superscalar register-renaming for a stack-addressed architectureSUDHAKAR RANGANATHAN·Filed 2009·Granted Sep 17, 2013·1 cites·20 claims
- 0947US9189412B2Apparatus and method for operating a processor with an operation cacheMIPS TECH INC·Filed 2013·Granted Nov 17, 2015·0 cites·5 claims
- 1046US10540179B2Apparatus and method for bonding branch instruction with architectural delay slotMIPS TECH LLC·Filed 2013·Granted Jan 21, 2020·0 cites·10 claims
- 1144US2014281413A1Superforwarding ProcessorMIPS TECH INC·Filed 2013·Application pending·0 cites
- 1243US2014258697A1Apparatus and Method for Transitive Instruction SchedulingMIPS TECH INC·Filed 2013·Application pending·0 cites
- 1342US10671391B2Modeless instruction execution with 64/32-bit addressingMIPS TECH LLC·Filed 2015·Granted Jun 2, 2020·0 cites·23 claims
- 1442US2014258667A1Apparatus and Method for Memory Operation BondingMIPS TECH INC·Filed 2013·Application pending·0 cites
- 1539US10768930B2Processor supporting arithmetic instructions with branch on overflow and methodsMIPS TECH LLC·Filed 2015·Granted Sep 8, 2020·0 cites·18 claims
- 1639US9740557B2Pipelined ECC-protected memory accessIMAGINATION TECH LTD·Filed 2015·Granted Aug 22, 2017·0 cites·13 claims
- 1737US2012005459A1Processor having increased performance and energy saving via move eliminationFLEISCHMAN JAY·Filed 2010·Application pending·0 cites
- 1834US2015227371A1Processors with Support for Compact Branch Instructions & MethodsIMAGINATION TECH LTD·Filed 2015·Application pending·0 cites
- 1933US2012166769A1Processor having increased performance via elimination of serial dependenciesFLEISCHMAN JAY E·Filed 2010·Application pending·0 cites
- 2032US2012191952A1Processor implementing scalar code optimizationFLEISCHMAN JAY E·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →