Inventor · disambiguated record
Ravishankar Sundaresan
Also filed as: SUNDARESAN RAVISHANKAR
32 granted patents·1 pending application·1,163 citations·filing 1984–2004
98Inventor score
Files withTEXAS INSTRUMENTS INC13CHARTERED SEMICONDUCTOR MFG9SGS THOMSON MICROELECTRONICS6ST MICROELECTRONICS INC4
Top patents by PatentIndex Score
33 records- 0197US4956307AThin oxide sidewall insulators for silicon-over-insulator transistorsTEXAS INSTRUMENTS INC·Filed 1988·Granted Sep 11, 1990·282 cites·16 claims
- 0296US5346839ASidewall doping technique for SOI transistorsTEXAS INSTRUMENTS INC·Filed 1993·Granted Sep 13, 1994·146 cites·8 claims
- 0390US5298782AStacked CMOS SRAM cell with polysilicon transistor loadSGS THOMSON MICROELECTRONICS·Filed 1991·Granted Mar 29, 1994·73 cites·20 claims
- 0489US5293053AElevated CMOSTEXAS INSTRUMENTS INC·Filed 1991·Granted Mar 8, 1994·77 cites·16 claims
- 0588US5276347AGate overlapping LDD structureSGS THOMSON MICROELECTRONICS·Filed 1991·Granted Jan 4, 1994·73 cites·8 claims
- 0683US4628589AMethod for fabricating stacked CMOS structuresTEXAS INSTRUMENTS INC·Filed 1984·Granted Dec 16, 1986·34 cites·8 claims
- 0781US5016070AStacked CMOS sRAM with vertical transistors and cross-coupled capacitorsTEXAS INSTRUMENTS INC·Filed 1990·Granted May 14, 1991·50 cites·11 claims
- 0879US5294823ASOI BICMOS processTEXAS INSTRUMENTS INC·Filed 1992·Granted Mar 15, 1994·52 cites·5 claims
- 0978US5102809ASOI BICMOS processTEXAS INSTRUMENTS INC·Filed 1990·Granted Apr 7, 1992·52 cites·7 claims
- 1075US5072276AElevated CMOSTEXAS INSTRUMENTS INC·Filed 1990·Granted Dec 10, 1991·56 cites·18 claims
- 1173US6297109B1Method to form shallow junction transistors while eliminating shorts due to junction spikingCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Oct 2, 2001·26 cites·16 claims
- 1273US5304504AMethod of forming a gate overlap LDD structureSGS THOMSON MICROELECTRONICS·Filed 1993·Granted Apr 19, 1994·30 cites·13 claims
- 1373US4656731AMethod for fabricating stacked CMOS transistors with a self-aligned silicide processTEXAS INSTRUMENTS INC·Filed 1985·Granted Apr 14, 1987·43 cites·11 claims
- 1469US6107642ASRAM cell with thin film transistor using two polysilicon layersCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Aug 22, 2000·30 cites·20 claims
- 1566US6531750B2Shallow junction transistors which eliminating shorts due to junction spikingCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Mar 11, 2003·9 cites·10 claims
- 1661US5721163AMethod of manufacture of thin film transistor SRAM device with a titanium nitride or silicide gateCHARTERED SEMICONDUCTOR MFG·Filed 1996·Granted Feb 24, 1998·16 cites·11 claims
- 1752US5702987AMethod of manufacture of self-aligned JFETCHARTERED SEMICONDUCTOR MFG·Filed 1996·Granted Dec 30, 1997·16 cites·27 claims
- 1850US6812142B1Method and interlevel dielectric structure for improved metal step coverageST MICROELECTRONICS INC·Filed 2000·Granted Nov 2, 2004·4 cites·16 claims
- 1950US5347152AStacked CMOS latch with cross-coupled capacitorsTEXAS INSTRUMENTS INC·Filed 1993·Granted Sep 13, 1994·13 cites·10 claims
- 2049US5686334AMethod of making SRAM cell with thin film transistor using two polysilicon layersCHARTERED SEMICONDUCTOR MFG·Filed 1996·Granted Nov 11, 1997·10 cites·20 claims
- 2148US5861643ASelf-aligned JFETCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Jan 19, 1999·11 cites·20 claims
- 2247US4950618AMasking scheme for silicon dioxide mesa formationTEXAS INSTRUMENTS INC·Filed 1989·Granted Aug 21, 1990·14 cites·8 claims
- 2346US5990528AThin film transistor with titanium nitride or refractory metal gate in SRAM device serving as source/drain contact electrode of an independent FETCHARTERED SEMICONDUCTOR MFG·Filed 1997·Granted Nov 23, 1999·7 cites·10 claims
- 2445US5554548AMethod of fabricating a one-sided polysilicon thin film transistorSGS THOMSON MICROELECTRONICS·Filed 1995·Granted Sep 10, 1996·8 cites·15 claims
- 2541US5292670ASidewall doping technique for SOI transistorsTEXAS INSTRUMENTS INC·Filed 1991·Granted Mar 8, 1994·7 cites·5 claims
- 2639USRE41670ESram cell fabrication with interlevel Dielectric planarizationST MICROELECTRONICS INC·Filed 2000·Granted Sep 14, 2010·0 cites·34 claims
- 2739US6566209B2Method to form shallow junction transistors while eliminating shorts due to junction spikingCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted May 20, 2003·0 cites·7 claims
- 2839US6190179B1Method of making a field effect transistor having a channel in an epitaxial silicon layerST MICROELECTRONICS INC·Filed 1995·Granted Feb 20, 2001·5 cites·14 claims
- 2939US5395785ASRAM cell fabrication with interlevel dielectric planarizationSGS THOMSON MICROELECTRONICS·Filed 1993·Granted Mar 7, 1995·7 cites·18 claims
- 3038US6753576B1Method of fabricating a one-sided polysilicon thin film transistorST MICROELECTRONICS INC·Filed 1994·Granted Jun 22, 2004·5 cites·4 claims
- 3136US5710461ASRAM cell fabrication with interlevel dielectric planarizationSGS THOMSON MICROELECTRONICS·Filed 1997·Granted Jan 20, 1998·4 cites·18 claims
- 3236US2004178446A1Method of forming asymmetrical polysilicon thin film transistorFiled 2004·Application pending·0 cites
- 3329US5723988ACMOS with parasitic bipolar transistorTEXAS INSTRUMENTS INC·Filed 1993·Granted Mar 3, 1998·3 cites·6 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →