Stacked CMOS sRAM with vertical transistors and cross-coupled capacitors

Abstract

A transistor cell (80) and enabling transistor (118) are provided. The transistor cell includes a trench transistor and a stacked transistor, with a cross-coupled capacitor between the gates of these transistors. The trench transistor includes a semiconductor region (98) functioning as a gate and first and second diffused regions (126, 135) as the source/drain regions therefor. The stacked transistor has a semiconductor layer (104) functioning as the gate and first and second doped regions (112, 114) within a semiconductor layer (110) functioning as the source/drain regions therefor. The stacked capacitor included herewith comprises semiconductor layer (104) and semiconductor region (98) having insulating layers (96, 102) therebetween.

What is claimed is: 
     
       1. An integrated device comprising: a semiconductive substrate having a first trench formed therein and having a first conductivity type;   first and second doped regions formed in said substrate each adjacent to said trench and separated by a first channel region;   a first insulating layer formed on the walls of said first trench;   a first gate formed on the walls of said trench over said insulating layer, said gate controlling current in said first channel region;   a second insulating layer formed on the walls of said trench and over said first gate;   a second gate formed on the walls of said trench and over said second insulating layer, said second gate and said first gate being capacitively coupled and said second gate being conductively connected to said second doped region;   a third insulating layer formed on said second gate; and   a semiconductive layer formed on said third insulating layer, a third and fourth doped region formed in said semiconductive layer, said third and fourth doped regions being separated by a second channel region and said second gate controlling current in said second channel region.   
     
     
       2. An integrated device as in claim 1 wherein said substrate comprises crystalline silicon. 
     
     
       3. An integrated device as in claim 1 wherein said semiconductive layer comprises polycrystalline silicon. 
     
     
       4. An integrated device as in claim 1 wherein said third doped region is conductively connected to said first gate. 
     
     
       5. An integrated device as in claim 5 further comprising: a second trench formed in said substrate, said second doped region extending to said second trench from said first trench;   a fifth doped region formed in said substrate adjacent to said second trench, said fifth doped region being separated from said second doped region by a third channel region; and   a gate formed in said second trench controlling current in said third channel region.   
     
     
       6. An integrated device which includes a pair of transistor cells, said integrated device comprising: a semiconductive of a first conductivity type, said semiconductor being the substrate for and defining a first trench for each one of said pair of transistor cells each of said transistor cells including:   first and second doped regions formed in said substrate, each adjacent to said trench and separated by a first channel region;   a first insulating layer formed on the walls of said first trench;   a first gate formed in said trench and over said insulating layer, said gate controlling current in said first channel region;   a second insulating layer formed on the walls of said trench and over said first gate;   a second gate formed on the walls of said trench and over said second insulating layer, said second gate and said first gate being capacitively coupled and said second gate being conductively connected to said second doped region;   a third insulating layer formed on said second gate;   a semiconductive layer formed on said third insulating layer, a third and fourth doped region formed in said semiconductive layer, said third and fourth doped regions being separated by a second channel region and said second gate controlling current in said second channel region; and   said first gates of said pair of cells conductively connected to said second gates of the other one of said pair of cells.   
     
     
       7. An integrated device as in claim 6 wherein for each of said transistor cells, said third doped region is conductively connected to said first gate. 
     
     
       8. An integrated device as in claim 6 wherein each one of said pair of transistor cells further comprises: a second trench formed in said substrate, said second doped region extending to said second trench from said first trench;   a fifth doped region formed in said substrate adjacent to said second trench, said fifth doped region being separated from said second doped region by a third channel region; and   a gate formed in said second trench controlling current in said third channel region.   
     
     
       9. An integrated device as in claim 6 wherein said substrate comprises crystalline silicon. 
     
     
       10. An integrated device as in claim 6 wherein said semiconductive layer comprises polycrystalline silicon. 
     
     
       11. An integrated device as in claim 6 wherein said third doped region of at least one of said pair of transistor cells is conductively connected to said first gate.