Inventor · disambiguated record
Ramesh C. Tekumalla
Also filed as: TEKUMALLA RAMESH C
24 granted patents·10 pending applications·137 citations·filing 2002–2014
95Inventor score
Top patents by PatentIndex Score
34 records- 0197US8788896B2Scan chain lockup latch with data input control responsive to scan enable signalTEKUMALLA RAMESH C·Filed 2012·Granted Jul 22, 2014·31 cites·18 claims
- 0291US8904255B2Integrated circuit having clock gating circuitry responsive to scan shift control signalTEKUMALLA RAMESH C·Filed 2012·Granted Dec 2, 2014·11 cites·19 claims
- 0389US8924801B2At-speed scan testing of interface functional logic of an embedded memory or other circuit coreLSI CORP·Filed 2013·Granted Dec 30, 2014·8 cites·20 claims
- 0487US8700962B2Scan test circuitry configured to prevent capture of potentially non-deterministic valuesTEKUMALLA RAMESH C·Filed 2012·Granted Apr 15, 2014·7 cites·20 claims
- 0587US8671320B2Integrated circuit comprising scan test circuitry with controllable number of capture pulsesTEKUMALLA RAMESH C·Filed 2011·Granted Mar 11, 2014·7 cites·20 claims
- 0687US8645778B2Scan test circuitry with delay defect bypass functionalityTEKUMALLA RAMESH C·Filed 2011·Granted Feb 4, 2014·7 cites·20 claims
- 0785US8850280B2Scan enable timing control for testing of scan cellsTEKUMALLA RAMESH C·Filed 2011·Granted Sep 30, 2014·6 cites·24 claims
- 0884US8726108B2Scan test circuitry configured for bypassing selected segments of a multi-segment scan chainTEKUMALLA RAMESH C·Filed 2012·Granted May 13, 2014·7 cites·20 claims
- 0983US8826087B2Scan circuitry for testing input and output functional paths of an integrated circuitLSI CORP·Filed 2012·Granted Sep 2, 2014·5 cites·25 claims
- 1082US8566658B2Low-power and area-efficient scan cell for integrated circuit testingTEKUMALLA RAMESH C·Filed 2011·Granted Oct 22, 2013·6 cites·22 claims
- 1181US8819508B2Scan test circuitry configured to prevent violation of multiplexer select signal constraints during scan testingLSI CORP·Filed 2012·Granted Aug 26, 2014·5 cites·23 claims
- 1277US8812921B2Dynamic clock domain bypass for scan chainsTEKUMALLA RAMESH C·Filed 2011·Granted Aug 19, 2014·4 cites·18 claims
- 1375US8738978B2Efficient wrapper cell design for scan testing of integratedTEKUMALLA RAMESH C·Filed 2011·Granted May 27, 2014·4 cites·20 claims
- 1471US8751884B2Scan test circuitry with selectable transition launch modeTEKUMALLA RAMESH C·Filed 2012·Granted Jun 10, 2014·2 cites·20 claims
- 1567US6886145B2Reducing verification time for integrated circuit design including scan circuitsSUN MICROSYSTEMS INC·Filed 2002·Granted Apr 26, 2005·14 cites·5 claims
- 1666US8793546B2Integrated circuit comprising scan test circuitry with parallel reordered scan chainsTEKUMALLA RAMESH C·Filed 2011·Granted Jul 29, 2014·2 cites·15 claims
- 1763US8615693B2Scan test circuitry comprising scan cells with multiple scan inputsTEKUMALLA RAMESH C·Filed 2011·Granted Dec 24, 2013·1 cites·20 claims
- 1861US8898527B2At-speed scan testing of clock divider logic in a clock module of an integrated circuitLSI CORP·Filed 2013·Granted Nov 25, 2014·1 cites·20 claims
- 1959US6745374B2Algorithms for determining path coverages and activitySUN MICROSYSTEMS INC·Filed 2002·Granted Jun 1, 2004·9 cites·30 claims
- 2049US8799731B2Clock control for reducing timing exceptions in scan testing of an integrated circuitLSI CORP·Filed 2012·Granted Aug 5, 2014·0 cites·24 claims
- 2149US8677200B2Integrated circuit with transition control circuitry for limiting scan test signal transitions during scan testingTEKUMALLA RAMESH C·Filed 2011·Granted Mar 18, 2014·0 cites·20 claims
- 2247US9251916B2Integrated clock architecture for improved testingLSI CORP·Filed 2013·Granted Feb 2, 2016·0 cites·20 claims
- 2345US2014298123A1Scan Chain Reconfiguration and RepairLSI CORP·Filed 2013·Application pending·0 cites
- 2445US2016020158A1Systems and Methods for Self Test Circuit SecurityLSI CORP·Filed 2014·Application pending·0 cites
- 2542US2014365838A1Integrated circuit comprising test circuitry for testing fan-out paths of a test control primary inputLSI CORP·Filed 2013·Application pending·0 cites
- 2642US2014304562A1Method for Testing Paths to Pull-Up and Pull-Down of Input/Output PadsLSI CORP·Filed 2013·Application pending·0 cites
- 2741US2014149812A1Scan test circuitry with control circuitry configured to support a debug mode of operationLSI CORP·Filed 2012·Application pending·0 cites
- 2840US2014201584A1Scan test circuitry comprising at least one scan chain and associated reset multiplexing circuitryLSI CORP·Filed 2013·Application pending·0 cites
- 2938US9348593B2Instruction address encoding and decoding based on program construct groupsKRISHNAMOORTHY PRAKASH·Filed 2012·Granted May 24, 2016·0 cites·20 claims
- 3038US2013311843A1Scan controller configured to control signal values applied to signal lines of circuit core input interfaceTEKUMALLA RAMESH C·Filed 2012·Application pending·0 cites
- 3135US2013124594A1Divider circuitry with quotient prediction based on estimated partial remainderKRISHNAMOORTHY PRAKASH·Filed 2011·Application pending·0 cites
- 3235US2014281703A1Local Repair Signature Handling for Repairable MemoriesLSI CORP·Filed 2013·Application pending·0 cites
- 3333US8711013B2Coding circuitry for difference-based data transformationKRISHNAMOORTHY PRAKASH·Filed 2012·Granted Apr 29, 2014·0 cites·26 claims
- 3432US2013275824A1Scan-based capture and shift of interface functional signal values in conjunction with built-in self-testTEKUMALLA RAMESH C·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →