Inventor · disambiguated record
Raymond S. Tetrick
Also filed as: TETRICK RAYMOND · TETRICK RAYMOND S · TETRICK RAYMOND SCOTT
25 granted patents·6 pending applications·496 citations·filing 1983–2024
96Inventor score
Top patents by PatentIndex Score
31 records- 0192US4570220AHigh speed parallel bus and data transfer methodINTEL CORP·Filed 1983·Granted Feb 11, 1986·194 cites·21 claims
- 0285US10241710B2Multi-level memory with direct accessINTEL CORP·Filed 2017·Granted Mar 26, 2019·4 cites·28 claims
- 0385US9678666B2Techniques to configure a solid state drive to operate in a storage mode or a memory modeINTEL CORP·Filed 2015·Granted Jun 13, 2017·3 cites·24 claims
- 0485US9190124B2Multi-level memory with direct accessFANNING BLAISE·Filed 2011·Granted Nov 17, 2015·7 cites·36 claims
- 0583US9098402B2Techniques to configure a solid state drive to operate in a storage mode or a memory modeINTEL CORP·Filed 2012·Granted Aug 4, 2015·5 cites·26 claims
- 0682US9430151B2Multi-level memory with direct accessINTEL CORP·Filed 2015·Granted Aug 30, 2016·2 cites·26 claims
- 0779US6003112AMemory controller and method for clearing or copying memory utilizing register files to store address informationINTEL CORP·Filed 1997·Granted Dec 14, 1999·86 cites·24 claims
- 0878US6598199B2Memory array organizationINTEL CORP·Filed 2001·Granted Jul 22, 2003·27 cites·16 claims
- 0977US7502877B2Dynamically setting routing information to transfer input output data directly into processor caches in a multi processor systemINTEL CORP·Filed 2007·Granted Mar 10, 2009·7 cites·17 claims
- 1075US9703502B2Multi-level memory with direct accessINTEL CORP·Filed 2016·Granted Jul 11, 2017·1 cites·26 claims
- 1174US7231470B2Dynamically setting routing information to transfer input output data directly into processor caches in a multi processor systemINTEL CORP·Filed 2003·Granted Jun 12, 2007·17 cites·14 claims
- 1274US4807109AHigh speed synchronous/asynchronous local bus and data transfer methodINTEL CORP·Filed 1987·Granted Feb 21, 1989·58 cites·16 claims
- 1371US7360027B2Method and apparatus for initiating CPU data prefetches by an external agentINTEL CORP·Filed 2004·Granted Apr 15, 2008·16 cites·53 claims
- 1467US12474848B2Techniques for memory resource control using memory resource partitioning and monitoringAMPERE COMPUTING LLC·Filed 2023·Granted Nov 18, 2025·0 cites·20 claims
- 1566US12058044B1Apparatus and method of routing a request in a mesh networkAMPERE COMPUTING LLC·Filed 2023·Granted Aug 6, 2024·0 cites·12 claims
- 1666US11042297B2Techniques to configure a solid state drive to operate in a storage mode or a memory modeINTEL CORP·Filed 2019·Granted Jun 22, 2021·0 cites·25 claims
- 1766US10817201B2Multi-level memory with direct accessINTEL CORP·Filed 2019·Granted Oct 27, 2020·0 cites·31 claims
- 1864US7089399B2Adaptive prefetch of I/O data blocksINTEL CORP·Filed 2003·Granted Aug 8, 2006·8 cites·9 claims
- 1962US8386701B2Apparatus and method for multi-level cache utilizationINTEL CORP·Filed 2012·Granted Feb 26, 2013·1 cites·9 claims
- 2062US7783809B2Virtualization of pin functionality in a point-to-point interfaceINTEL CORP·Filed 2005·Granted Aug 24, 2010·2 cites·24 claims
- 2161US10296217B2Techniques to configure a solid state drive to operate in a storage mode or a memory modeINTEL CORP·Filed 2017·Granted May 21, 2019·0 cites·25 claims
- 2261US6006301AMulti-delivery scheme interrupt routerINTEL CORP·Filed 1997·Granted Dec 21, 1999·37 cites·30 claims
- 2359US6757798B2Method and apparatus for arbitrating deferred read requestsINTEL CORP·Filed 2001·Granted Jun 29, 2004·6 cites·15 claims
- 2456US2025291735A1Multi-core processor-based system implementing directed page table entry invalidationAMPERE COMPUTING LLC·Filed 2024·Application pending·0 cites
- 2553US2024354110A1Runtime adaptive prefetching in a many-core systemAMPERE COMPUTING LLC·Filed 2024·Application pending·0 cites
- 2653US2025130852A1Apparatus and method of workload throttling in a mesh networkAMPERE COMPUTING LLC·Filed 2023·Application pending·0 cites
- 2746US6622212B1Adaptive prefetch of I/O data blocksINTEL CORP·Filed 1999·Granted Sep 16, 2003·15 cites·20 claims
- 2845US2005210229A1Method and system for configuration of processor integrated devices in multi-processor systemsSETHI PRASHANT·Filed 2004·Application pending·0 cites
- 2945US2005223383A1Methods and apparatus for reserving an execution threadTETRICK RAYMOND S·Filed 2004·Application pending·0 cites
- 3042US2006294277A1Message signaled interrupt redirectionTETRICK RAYMOND S·Filed 2005·Application pending·0 cites
- 3130US6912556B1Silicon averaging measurement circuitINTEL CORP·Filed 1998·Granted Jun 28, 2005·0 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →