Inventor · disambiguated record
Ramanand Venkata
Also filed as: VENKATA RAMANAND
52 granted patents·1 pending application·764 citations·filing 2002–2020
98Inventor score
Top patents by PatentIndex Score
53 records- 0198US6750675B2Programmable logic devices with multi-standard byte synchronization and channel alignment for communicationALTERA CORP·Filed 2002·Granted Jun 15, 2004·108 cites·20 claims
- 0295US7366267B1Clock data recovery with double edge clocking based phase detector and serializer/deserializerALTERA CORP·Filed 2002·Granted Apr 29, 2008·77 cites·37 claims
- 0393US6724328B1Byte alignment for serial data receiverALTERA CORP·Filed 2003·Granted Apr 20, 2004·99 cites·29 claims
- 0492US7046174B1Byte alignment for serial data receiverALTERA CORP·Filed 2005·Granted May 16, 2006·31 cites·25 claims
- 0590US7272677B1Multi-channel synchronization for programmable logic device serial interfaceALTERA CORP·Filed 2003·Granted Sep 18, 2007·42 cites·70 claims
- 0689US9503057B1Clock grid for integrated circuitALTERA CORP·Filed 2013·Granted Nov 22, 2016·9 cites·28 claims
- 0789US8812893B1Apparatus and methods for low-skew channel bondingVENKATA RAMANAND·Filed 2012·Granted Aug 19, 2014·14 cites·13 claims
- 0889US8571059B1Apparatus and methods for serial interfaces with shared datapathsZALIZNYAK ARCH·Filed 2011·Granted Oct 29, 2013·17 cites·18 claims
- 0989US6854044B1Byte alignment circuitryALTERA CORP·Filed 2002·Granted Feb 8, 2005·47 cites·21 claims
- 1088US9606573B1Configurable clock grid structuresALTERA CORP·Filed 2015·Granted Mar 28, 2017·6 cites·25 claims
- 1188US7305058B1Multi-standard clock rate matching circuitryALTERA CORP·Filed 2002·Granted Dec 4, 2007·25 cites·18 claims
- 1287US8692595B1Transceiver circuitry with multiple phase-locked loopsALTERA CORP·Filed 2013·Granted Apr 8, 2014·8 cites·21 claims
- 1387US6888376B1Multiple data rates in programmable logic device serial interfaceALTERA CORP·Filed 2003·Granted May 3, 2005·34 cites·38 claims
- 1485US7848318B2Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuitsALTERA CORP·Filed 2006·Granted Dec 7, 2010·11 cites·13 claims
- 1584US8570197B2Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuitsNGUYEN TOAN THANH·Filed 2010·Granted Oct 29, 2013·6 cites·7 claims
- 1684US6842034B1Selectable dynamic reconfiguration of programmable embedded IPALTERA CORP·Filed 2003·Granted Jan 11, 2005·24 cites·18 claims
- 1781US7292070B1Programmable PPM detectorALTERA CORP·Filed 2005·Granted Nov 6, 2007·13 cites·13 claims
- 1880US10649944B2Configuration via high speed serial linkALTERA CORP·Filed 2017·Granted May 12, 2020·2 cites·25 claims
- 1980US7436210B2Next generation 8B10B architectureALTERA CORP·Filed 2007·Granted Oct 14, 2008·8 cites·20 claims
- 2080US7180972B1Clock signal circuitry for multi-protocol high-speed serial interface circuitryALTERA CORP·Filed 2002·Granted Feb 20, 2007·24 cites·45 claims
- 2180US6867616B1Programmable logic device serial interface having dual-use phase-locked loop circuitryALTERA CORP·Filed 2003·Granted Mar 15, 2005·22 cites·33 claims
- 2279US7443922B1Circuitry for padded communication protocolsALTERA CORP·Filed 2003·Granted Oct 28, 2008·13 cites·27 claims
- 2376US8581653B1Techniques for providing clock signals in clock networksMARURI VICTOR·Filed 2011·Granted Nov 12, 2013·6 cites·20 claims
- 2476US7138837B2Digital phase locked loop circuitry and methodsALTERA CORP·Filed 2003·Granted Nov 21, 2006·23 cites·28 claims
- 2575US7131024B1Multiple transmit data rates in programmable logic device serial interfaceALTERA CORP·Filed 2003·Granted Oct 31, 2006·20 cites·27 claims
- 2674US9843332B1Clock grid for integrated circuitALTERA CORP·Filed 2017·Granted Dec 12, 2017·1 cites·20 claims
- 2772US8994425B2Techniques for aligning and reducing skew in serial data signalsVENKATA RAMANAND·Filed 2012·Granted Mar 31, 2015·3 cites·21 claims
- 2871US9690741B2Configuration via high speed serial linkALTERA CORP·Filed 2013·Granted Jun 27, 2017·2 cites·22 claims
- 2971US7698482B2Multiple data rates in integrated circuit device serial interfaceALTERA CORP·Filed 2005·Granted Apr 13, 2010·6 cites·24 claims
- 3071US7656187B2Multi-channel communication circuitry for programmable logic device integrated circuits and the likeALTERA CORP·Filed 2005·Granted Feb 2, 2010·6 cites·23 claims
- 3170US7538578B2Multiple data rates in programmable logic device serial interfaceALTERA CORP·Filed 2005·Granted May 26, 2009·6 cites·45 claims
- 3264US9024673B1Techniques for providing clock signals in an integrated circuitALTERA CORP·Filed 2013·Granted May 5, 2015·1 cites·20 claims
- 3364US7659838B2Deserializer circuitry for high-speed serial data receivers on programmable logic device integrated circuitsALTERA CORP·Filed 2006·Granted Feb 9, 2010·5 cites·18 claims
- 3463US6963223B2Programmable logic devices with multi-standard byte synchronization and channel alignment for communicationALTERA CORP·Filed 2004·Granted Nov 8, 2005·7 cites·10 claims
- 3562US7039787B1Byte alignment circuitryALTERA CORP·Filed 2004·Granted May 2, 2006·6 cites·20 claims
- 3661US9077330B2Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuitsALTERA CORP·Filed 2013·Granted Jul 7, 2015·1 cites·20 claims
- 3761US7869553B1Digital phase locked loop circuitry and methodsALTERA CORP·Filed 2004·Granted Jan 11, 2011·4 cites·18 claims
- 3861US2021011875A1Configuration via high speed serial linkALTERA CORP·Filed 2020·Application pending·0 cites
- 3960US7646217B2Programmable logic device with serial interconnectALTERA CORP·Filed 2006·Granted Jan 12, 2010·3 cites·19 claims
- 4060US7310399B1Clock signal circuitry for multi-protocol high-speed serial interface circuitryALTERA CORP·Filed 2007·Granted Dec 18, 2007·1 cites·24 claims
- 4160US7183797B2Next generation 8B10B architectureALTERA CORP·Filed 2004·Granted Feb 27, 2007·5 cites·25 claims
- 4259US7071726B1Selectable dynamic reconfiguration of programmable embedded IPALTERA CORP·Filed 2004·Granted Jul 4, 2006·7 cites·20 claims
- 4357US9660630B1Clock grid for integrated circuitALTERA CORP·Filed 2016·Granted May 23, 2017·0 cites·20 claims
- 4456US7151470B1Data converter with multiple conversions for padded-protocol interfaceALTERA CORP·Filed 2004·Granted Dec 19, 2006·8 cites·30 claims
- 4550US9438272B1Digital phase locked loop circuitry and methodsALTERA CORP·Filed 2014·Granted Sep 6, 2016·0 cites·20 claims
- 4649US8923440B1Circuitry for padded communication protocolsVENKATA RAMANAND·Filed 2008·Granted Dec 30, 2014·0 cites·34 claims
- 4748US8804890B2Digital phase locked loop circuitry and methodsALTERA CORP·Filed 2013·Granted Aug 12, 2014·0 cites·20 claims
- 4848US7577166B2Programmable logic devices with multi-standard byte synchronization and channel alignment for communicationALTERA CORP·Filed 2005·Granted Aug 18, 2009·0 cites·20 claims
- 4946US9515880B1Integrated circuits with clock selection circuitryVENKATA RAMANAND·Filed 2011·Granted Dec 6, 2016·0 cites·21 claims
- 5046US8462908B2Digital phase locked loop circuitry and methodsVENKATA RAMANAND·Filed 2010·Granted Jun 11, 2013·0 cites·12 claims
Showing the top 50 of 53 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →