Configuration via high speed serial link

Abstract

Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.

1 - 22 . (canceled) 
     
     
         23 . An integrated circuit, comprising:
 a memory that stores configuration data to enable a field programmable gate array (FPGA) fabric to be programmed with the configuration data;   peripheral component interconnect express (PCIe) circuitry that receives the configuration data via a PCIe interface; and   state machine that receives the configuration data from the PCIe circuitry and provides the configuration data to the memory to program the FPGA fabric, wherein the state machine comprises a dedicated communication link with the PCIe circuitry.   
     
     
         24 . The integrated circuit of  claim 23 , wherein the FPGA fabric is non-operational when programming the FPGA fabric. 
     
     
         25 . The integrated circuit of  claim 23 , wherein the PCIe circuitry receives the configuration data in blocks until entire configuration data is received. 
     
     
         26 . The integrated circuit of  claim 23 , wherein the PCIe circuitry comprises a number of high speed serial lanes less than sixteen. 
     
     
         27 . The integrated circuit of  claim 23 , wherein the PCIe circuitry comprises less than sixteen high speed serial lanes for receiving the configuration data. 
     
     
         28 . The integrated circuit of  claim 23 , wherein the PCIe circuitry comprises one serial lane, two serial lanes, or four serial lanes for receiving the configuration data. 
     
     
         29 . The integrated circuit of  claim 23 , wherein the PCIe circuitry receives the configuration data from a master host device. 
     
     
         30 . The integrated circuit of  claim 23 , wherein the state machine corresponds to a master device and the memory corresponds to a slave device controlled by the master device. 
     
     
         31 . A system, comprising:
 a host processor that transmits field programmable gate array (FPGA) bitstream data using peripheral component interconnect express (PCIe); and   FPGA circuitry on an FPGA that:
 receives the FPGA bitstream data over the PCIe using a serial controller, wherein the FPGA circuitry comprises a dedicated communication link with the serial controller; 
 loads the FPGA bitstream data on the FPGA; and 
 operates FPGA programmable logic of the FPGA in accordance with the FPGA bitstream data loaded on the FPGA. 
   
     
     
         32 . The system of  claim 31 , wherein the PCIe comprises a number of high speed serial lanes between one and sixteen. 
     
     
         33 . The system of  claim 31 , wherein the PCIe comprises less than sixteen high speed serial lanes for receiving the FPGA bitstream data. 
     
     
         34 . The system of  claim 31 , wherein the PCIe comprises one serial lane, two serial lanes, or four serial lanes for receiving the FPGA bitstream data. 
     
     
         35 . The system of  claim 31 , wherein the FPGA circuitry is non-operational when programming the FPGA circuitry. 
     
     
         36 . The system of  claim 31 , wherein the PCIe receives the FPGA bitstream data in blocks until entire configuration data is received. 
     
     
         37 . A system, comprising:
 a master host device that sends field programmable gate array (FPGA) bitstream data to configure a slave FPGA device, using peripheral component interconnect express (PCIe);   a master state machine on the FPGA device that:
 receives the FPGA bitstream data from a slave serial circuit that receives the FPGA bitstream data over PCIe using one or more serial lanes; and 
 sends the FPGA bitstream to a memory of the system to program FPGA logic fabric of the FPGA device. 
   
     
     
         38 . The system of  claim 37 , wherein the master state machine on the FPGA device comprises a dedicated communication link with a slave serial circuit. 
     
     
         39 . The system of  claim 37 , wherein the one or more serial lanes comprise a number of high speed serial lanes between one and sixteen. 
     
     
         40 . The system of  claim 39 , wherein the one or more serial lanes comprise less than sixteen high speed serial lanes for receiving the FPGA bitstream. 
     
     
         41 . The system of  claim 37 , wherein the one or more serial lanes comprise one serial lane, two serial lanes, or four serial lanes for receiving the FPGA bitstream. 
     
     
         42 . The system of  claim 37 , wherein the PCIe receives the FPGA bitstream from a master host device.