Inventor · disambiguated record
Ramnath Venkatraman
Also filed as: VENKATRAMAN RAMNATH
34 granted patents·6 pending applications·1,603 citations·filing 1996–2013
98Inventor score
Top patents by PatentIndex Score
40 records- 0198US8178909B2Integrated circuit cell architecture configurable for memory or logic elementsVENKATRAMAN RAMNATH·Filed 2011·Granted May 15, 2012·115 cites·6 claims
- 0298US8044437B1Integrated circuit cell architecture configurable for memory or logic elementsLSI LOGIC CORP·Filed 2005·Granted Oct 25, 2011·115 cites·12 claims
- 0397US7404154B1Basic cell architecture for structured application-specific integrated circuitsLSI CORP·Filed 2005·Granted Jul 22, 2008·130 cites·16 claims
- 0495US6713381B2Method of forming semiconductor device including interconnect barrier layersMOTOROLA INC·Filed 2002·Granted Mar 30, 2004·135 cites·13 claims
- 0595US6218302B1Method for forming a semiconductor deviceMOTOROLA INC·Filed 1998·Granted Apr 17, 2001·222 cites·22 claims
- 0695US6174810B1Copper interconnect structure and method of formationMOTOROLA INC·Filed 1998·Granted Jan 16, 2001·235 cites·13 claims
- 0791US6980462B1Memory cell architecture for reduced routing congestionLSI LOGIC CORP·Filed 2003·Granted Dec 27, 2005·58 cites·36 claims
- 0889US7006370B1Memory cell architectureLSI LOGIC CORP·Filed 2003·Granted Feb 28, 2006·50 cites·30 claims
- 0989US6093966ASemiconductor device with a copper barrier layer and formation thereofMOTOROLA INC·Filed 1998·Granted Jul 25, 2000·116 cites·31 claims
- 1089US5814557AMethod of forming an interconnect structureMOTOROLA INC·Filed 1996·Granted Sep 29, 1998·124 cites·7 claims
- 1185US7304874B2Compact ternary and binary CAM bitcell architecture with no enclosed diffusion areasLSI CORP·Filed 2005·Granted Dec 4, 2007·18 cites·16 claims
- 1283US8429586B2Basic cell architecture for structured ASICsVENKATRAMAN RAMNATH·Filed 2012·Granted Apr 23, 2013·5 cites·5 claims
- 1382US7440356B2Modular design of multiport memory bitcellsLSI CORP·Filed 2006·Granted Oct 21, 2008·13 cites·20 claims
- 1482US6566171B1Fuse construction for integrated circuit structure having low dielectric constant dielectric materialLSI LOGIC CORP·Filed 2001·Granted May 20, 2003·30 cites·20 claims
- 1580US5677244AMethod of alloying an interconnect structure with copperMOTOROLA INC·Filed 1996·Granted Oct 14, 1997·62 cites·20 claims
- 1679US7042747B1Ternary CAM bitcellsLSI LOGIC CORP·Filed 2005·Granted May 9, 2006·13 cites·20 claims
- 1775US8738940B2Power controller for SoC power gating applicationsVENKATRAMAN RAMNATH·Filed 2011·Granted May 27, 2014·5 cites·17 claims
- 1875US8411399B2Defectivity-immune technique of implementing MIM-based decoupling capacitorsVENKATRAMAN RAMNATH·Filed 2010·Granted Apr 2, 2013·4 cites·20 claims
- 1972US9158319B2Closed-loop adaptive voltage scaling for integrated circuitsLSI CORP·Filed 2013·Granted Oct 13, 2015·4 cites·20 claims
- 2072US6442061B1Single channel four transistor SRAMLSI LOGIC CORP·Filed 2001·Granted Aug 27, 2002·15 cites·12 claims
- 2171US7082067B2Circuit for verifying the write speed of SRAM cellsLSI LOGIC CORP·Filed 2004·Granted Jul 25, 2006·17 cites·36 claims
- 2271US6806551B2Fuse construction for integrated circuit structure having low dielectric constant dielectric materialLSI LOGIC CORP·Filed 2003·Granted Oct 19, 2004·15 cites·4 claims
- 2370US6664141B1Method of forming metal fuses in CMOS processes with copper interconnectLSI LOGIC CORP·Filed 2001·Granted Dec 16, 2003·14 cites·21 claims
- 2468US6828653B1Method of forming metal fuses in CMOS processes with copper interconnectLSI LOGIC CORP·Filed 2003·Granted Dec 7, 2004·12 cites·6 claims
- 2567US8112734B2Optimization with adaptive body biasingMBOUOMBOUO BENJAMIN·Filed 2008·Granted Feb 7, 2012·4 cites·20 claims
- 2662US8589853B2Total power optimization for a logic integrated circuitMBOUOMBOUO BENJAMIN·Filed 2011·Granted Nov 19, 2013·1 cites·8 claims
- 2760US5783485AProcess for fabricating a metallized interconnectMOTOROLA INC·Filed 1996·Granted Jul 21, 1998·27 cites·16 claims
- 2859US7869251B2SRAM based one-time-programmable memoryLSI CORP·Filed 2008·Granted Jan 11, 2011·4 cites·18 claims
- 2959US6077768AProcess for fabricating a multilevel interconnectMOTOROLA INC·Filed 1996·Granted Jun 20, 2000·24 cites·14 claims
- 3053US6934174B2Reconfigurable memory arraysLSI LOGIC CORP·Filed 2003·Granted Aug 23, 2005·5 cites·26 claims
- 3153US2014040842A1Total power optimization for a logic integrated circuitLSI CORP·Filed 2013·Application pending·0 cites
- 3251US7069535B2Optical proximity correction method using weighted prioritiesLSI LOGIC CORP·Filed 2003·Granted Jun 27, 2006·4 cites·27 claims
- 3348US7006369B2Design and use of a spacer cell to support reconfigurable memoriesLSI LOGIC CORP·Filed 2003·Granted Feb 28, 2006·7 cites·26 claims
- 3448US2014028364A1Critical path monitor hardware architecture for closed loop adaptive voltage scaling and method of operation thereofVENKATRAMAN RAMNATH·Filed 2012·Application pending·0 cites
- 3548US2013166931A1Reducing power consumption of memoryCASTAGNETTI RUGGERO·Filed 2011·Application pending·0 cites
- 3644US8166440B1Basic cell architecture for structured application-specific integrated circuitsVENKATRAMAN RAMNATH·Filed 2008·Granted Apr 24, 2012·0 cites·6 claims
- 3742US2013166930A1Reducing power consumption of memoryZHOU TING·Filed 2011·Application pending·0 cites
- 3839US2013154109A1Method of lowering capacitances of conductive apertures and an interposer capable of being reverse biased to achieve reduced capacitanceVENKATRAMAN RAMNATH·Filed 2011·Application pending·0 cites
- 3935US8624352B2Mitigation of detrimental breakdown of a high dielectric constant metal-insulator-metal capacitor in a capacitor bankWEIR BONNIE E·Filed 2010·Granted Jan 7, 2014·0 cites·20 claims
- 4027US2002000665A1Semiconductor device conductive bump and interconnect barrierFiled 1999·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →