Semiconductor device conductive bump and interconnect barrier

Abstract

An interconnect overlies a semiconductor device substrate ( 10 ). In one embodiment, a conductive barrier layer overlies a portion of the interconnect, a passivation layer ( 92 ) overlies the conductive barrier layer and the passivation layer ( 92 ) has an opening that exposes portions of the conductive barrier layer ( 82 ). In an alternate embodiment a passivation layer ( 22 ) overlies the interconnect, the passivation layer ( 22 ) has an opening ( 24 ) that exposes the interconnect and a conductive barrier layer ( 32 ) overlies the interconnect within the opening ( 24 ).

What is claimed is:  
     
         1 . A semiconductor device, comprising: 
 a first interconnect that overlies a semiconductor device substrate;    a insulating barrier layer that overlies the first interconnect;    a second interconnect that overlies portions of the first interconnect and the insulating barrier layer;    a conductive barrier layer that overlies a portion the second interconnect, the conductive barrier layer extending beyond an edge region of the portion of the second interconnect; and    a passivation layer that overlies the conductive barrier layer, the passivation layer having an opening that exposes portions of the conductive barrier layer.    
     
     
         2 . The semiconductor device of  claim 1 , wherein the second interconnect includes mostly copper.  
     
     
         3 . The semiconductor device of  claim 1 , wherein the conductive barrier layer includes a refractory metal nitride.  
     
     
         4 . The semiconductor device of  claim 1 , wherein the conductive barrier layer includes a material selected from a group consisting of titanium, tantalum, tungsten, iridium, and nickel.  
     
     
         5 . The semiconductor device of  claim 1 , further comprising an oxidation-resistant layer that overlies the conductive barrier layer.  
     
     
         6 . The semiconductor device of  claim 5 , wherein the oxidation-resistant layer includes nitrogen.  
     
     
         7 . The semiconductor device of  claim 5 , wherein the oxidation-resistant layer is a silicon layer.  
     
     
         8 . The semiconductor device of  claim 1 , wherein the portion of the second interconnect is further characterized as a bond pad.  
     
     
         9 . The semiconductor device of  claim 8 , wherein a portion of the conductive barrier layer is a laser-alterable connection between at least two conductive regions.  
     
     
         10 . The semiconductor device of  claim 8 , further comprising 
 a conductive bump that overlies the bond pad.    
     
     
         11 . A semiconductor device, comprising: 
 an interconnect over a semiconductor device substrate;    a passivation layer that overlies the interconnect, the passivation layer having an opening that exposes a portion of the interconnect; and    a conductive barrier layer within the opening that overlies the portion of the interconnect.    
     
     
         12 . The semiconductor device of  claim 11 , wherein the conductive barrier layer covers a sidewall portion of the opening.  
     
     
         13 . The semiconductor device of  claim 12 , wherein the conductive barrier layer extends over a surface portion of the passivation layer adjacent the sidewall portion.  
     
     
         14 . The semiconductor device of  claim 11 , wherein the interconnect includes mostly copper.  
     
     
         15 . The semiconductor device of  claim 11 , wherein the conductive barrier layer includes a refractory metal nitride.  
     
     
         16 . The semiconductor device of  claim 11 , wherein the conductive barrier layer includes a material selected from a group consisting of tantalum, titanium, tungsten, iridium, and nickel.  
     
     
         17 . The semiconductor device of  claim 11 , further comprising forming an oxidation-resistant layer over the conductive barrier layer.  
     
     
         18 . The semiconductor device of  claim 17 , wherein the oxidation-resistant layer includes nitrogen.  
     
     
         19 . The semiconductor device of  claim 17 , wherein the oxidation-resistant layer is a silicon layer.  
     
     
         20 . The semiconductor device of  claim 11 , further comprising a conductive bump over the conductive barrier layer.  
     
     
         21 . A method of forming a semiconductor device comprising: 
 forming a first interconnect overlying a semiconductor device substrate;    forming an insulating barrier layer overlying the first interconnect;    forming a second interconnect overlying portions of the first interconnect and the insulating barrier layer;    forming a conductive barrier layer overlying a portion of the second interconnect, the conductive barrier layer extending beyond an edge region of the portion of the second interconnect;    forming a passivation layer overlying the conductive barrier layer; and    forming an opening in the passivation layer, wherein the opening exposes portions of the conductive barrier layer.    
     
     
         22 . The method of  claim 21 , further comprising forming an oxidation-resistant layer overlying conductive barrier layer.  
     
     
         23 . The method of  claim 22 , wherein the oxidation-resistant layer includes a material selected from a group consisting of nitrogen and silicon.  
     
     
         24 . The method of  claim 21 , wherein a portion of the conductive barrier layer forms a laser-alterable connection between at least two conductive regions.  
     
     
         25 . The method of  claim 21 , wherein forming an opening in the passivation layer further comprises: 
 forming a partial opening in the passivation layer, wherein a depth of the partial opening is less than a thickness of the passivation layer in a region of the passivation layer where the partial opening is formed;    forming a die coat layer over the passivation layer;    forming an opening in the die coat layer, wherein forming the opening in the die coat layer exposes the partial opening in the passivation layer; and    etching the partial opening in the passivation layer to expose an underlying layer after forming an opening in the die coat layer.    
     
     
         26 . The method of  claim 21 , further comprising: 
 removing a portion of the conductive barrier layer after forming an opening in the passivation layer, wherein the portion of the conductive barrier layer has a depth; and    forming a conductive bump over the conductive barrier layer after removing a portion of the conductive barrier layer.    
     
     
         27 . The method of  claim 26 , wherein the depth is in a range of approximately 20-40 nanometers.  
     
     
         28 . A method of forming a semiconductor device, comprising: 
 forming an interconnect over a semiconductor device substrate;    forming a passivation layer over the interconnect;    forming an opening in the passivation layer, the opening exposing portions of the interconnect; and    forming a conductive barrier layer within the opening, the conductive barrier layer overlying exposed portions of the interconnect.    
     
     
         29 . The method of  claim 28 , further comprising forming an oxidation-resistant layer over the conductive barrier layer, wherein the oxidation-resistant layer includes a material selected from a group consisting of nitrogen and silicon.  
     
     
         30 . The method of  claim 28 , wherein the conductive barrier layer covers a sidewall portion of the opening and extends over a surface portion of the passivation layer adjacent the sidewall portion.  
     
     
         31 . The method of  claim 28 , wherein the interconnect includes copper.