Inventor · disambiguated record
Richard M. Barth
Also filed as: BARTH RICHARD M · BARTH RICHARD MAURICE · DILLON LEGAL REPRESENTATIVE NA
125 granted patents·9 pending applications·7,569 citations·filing 1989–2012
99Inventor score
Top patents by PatentIndex Score
134 records- 0199US6701446B2Power control system for synchronous memory deviceRAMBUS INC·Filed 2001·Granted Mar 2, 2004·184 cites·40 claims
- 0299US6321282B1Apparatus and method for topography dependent signalingRAMBUS INC·Filed 1999·Granted Nov 20, 2001·360 cites·50 claims
- 0398US7581121B2System for a memory device having a power down mode and methodRAMBUS INC·Filed 2005·Granted Aug 25, 2009·76 cites·21 claims
- 0498US6839266B1Memory module with offset data lines and bit line swizzle configurationRAMBUS INC·Filed 2002·Granted Jan 4, 2005·189 cites·12 claims
- 0598US6684263B2Apparatus and method for topography dependent signalingRAMBUS INC·Filed 2003·Granted Jan 27, 2004·127 cites·52 claims
- 0698US6516365B2Apparatus and method for topography dependent signalingRAMBUS INC·Filed 2001·Granted Feb 4, 2003·148 cites·32 claims
- 0798US6401167B1High performance cost optimized memoryRAMBUS INC·Filed 1998·Granted Jun 4, 2002·168 cites·67 claims
- 0898US6343042B1DRAM core refresh with reduced spike currentRAMBUS INC·Filed 2000·Granted Jan 29, 2002·99 cites·9 claims
- 0998US6310814B1Rambus DRAM (RDRAM) apparatus and method for performing refresh operationsRAMBUS INC·Filed 2000·Granted Oct 30, 2001·195 cites·40 claims
- 1098US6154821AMethod and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domainRAMBUS INC·Filed 1998·Granted Nov 28, 2000·237 cites·24 claims
- 1198US5748914AProtocol for communication with dynamic memoryRAMBUS INC·Filed 1995·Granted May 5, 1998·227 cites·19 claims
- 1297US7287119B2Integrated circuit memory device with delayed write command processingRAMBUS INC·Filed 2007·Granted Oct 23, 2007·40 cites·23 claims
- 1397US7210015B2Memory device having at least a first and a second operating modeRAMBUS INC·Filed 2005·Granted Apr 24, 2007·37 cites·24 claims
- 1497US7197611B2Integrated circuit memory device having write latency functionRAMBUS INC·Filed 2005·Granted Mar 27, 2007·54 cites·27 claims
- 1597US7174400B2Integrated circuit device that stores a value representative of an equalization co-efficient settingRAMBUS INC·Filed 2005·Granted Feb 6, 2007·34 cites·33 claims
- 1697US6266292B1DRAM core refresh with reduced spike currentRAMBUS INC·Filed 2000·Granted Jul 24, 2001·82 cites·46 claims
- 1797US6075744ADram core refresh with reduced spike currentRAMBUS INC·Filed 1998·Granted Jun 13, 2000·110 cites·11 claims
- 1897US5432823AMethod and circuitry for minimizing clock-data skew in a bus systemRAMBUS INC·Filed 1994·Granted Jul 11, 1995·504 cites·22 claims
- 1997US5430676ADynamic random access memory systemRAMBUS INC·Filed 1994·Granted Jul 4, 1995·164 cites·2 claims
- 2097US5337285AMethod and apparatus for power control in devicesRAMBUS INC·Filed 1993·Granted Aug 9, 1994·193 cites·36 claims
- 2196US7003639B2Memory controller with power management logicRAMBUS INC·Filed 2004·Granted Feb 21, 2006·126 cites·21 claims
- 2296US6842864B1Method and apparatus for configuring access times of memory devicesRAMBUS INC·Filed 2000·Granted Jan 11, 2005·99 cites·32 claims
- 2396US6597616B2DRAM core refresh with reduced spike currentRAMBUS INC·Filed 2002·Granted Jul 22, 2003·73 cites·32 claims
- 2496US6470405B2Protocol for communication with dynamic memoryRAMBUS INC·Filed 2001·Granted Oct 22, 2002·86 cites·37 claims
- 2596US6263448B1Power control system for synchronous memory deviceRAMBUS INC·Filed 1998·Granted Jul 17, 2001·186 cites·35 claims
- 2696US6075730AHigh performance cost optimized memory with delayed memory writesRAMBUS INC·Filed 1998·Granted Jun 13, 2000·182 cites·6 claims
- 2796US5511024ADynamic random access memory systemRAMBUS INC·Filed 1994·Granted Apr 23, 1996·134 cites·3 claims
- 2895US7546390B2Integrated circuit device and signaling method with topographic dependent equalization coefficientRAMBUS INC·Filed 2007·Granted Jun 9, 2009·20 cites·25 claims
- 2995US7130944B2Chip-to-chip communication system using an ac-coupled bus and devices employed in sameRAMBUS INC·Filed 2004·Granted Oct 31, 2006·77 cites·26 claims
- 3095US7032058B2Apparatus and method for topography dependent signalingRAMBUS INC·Filed 2005·Granted Apr 18, 2006·23 cites·31 claims
- 3195US7024502B2Apparatus and method for topography dependent signalingRAMBUS INC·Filed 2004·Granted Apr 4, 2006·45 cites·42 claims
- 3295US6868474B2High performance cost optimized memoryRAMBUS INC·Filed 2002·Granted Mar 15, 2005·58 cites·6 claims
- 3395US6854030B2Integrated circuit device having a capacitive coupling elementRAMBUS INC·Filed 2002·Granted Feb 8, 2005·95 cites·10 claims
- 3495US6591353B1Protocol for communication with dynamic memoryRAMBUS INC·Filed 2000·Granted Jul 8, 2003·88 cites·26 claims
- 3594US7287109B2Method of controlling a memory device having a memory coreRAMBUS INC·Filed 2004·Granted Oct 23, 2007·57 cites·25 claims
- 3694US6378018B1Memory device and system including a low power interfaceINTEL CORP·Filed 1998·Granted Apr 23, 2002·224 cites·32 claims
- 3793US8756395B2Controlling DRAM at time DRAM ready to receive command when exiting power downBARTH RICHARD M·Filed 2012·Granted Jun 17, 2014·12 cites·22 claims
- 3893US8214570B2Memory controller and method utilizing equalization co-efficient settingHOROWITZ MARK A·Filed 2011·Granted Jul 3, 2012·10 cites·30 claims
- 3993US8001305B2System and dynamic random access memory device having a receiverRAMBUS INC·Filed 2009·Granted Aug 16, 2011·12 cites·28 claims
- 4093US6810449B1Protocol for communication with dynamic memoryRAMBUS INC·Filed 2000·Granted Oct 26, 2004·75 cites·21 claims
- 4193US6405296B1Asynchronous request/synchronous data dynamic random access memoryRAMBUS INC·Filed 2000·Granted Jun 11, 2002·48 cites·51 claims
- 4293USRE37409EMemory and method for sensing sub-groups of memory elementsRAMBUS INC·Filed 2000·Granted Oct 16, 2001·68 cites·65 claims
- 4393US6021076AApparatus and method for thermal regulation in memory subsystemsRAMBUS INC·Filed 1998·Granted Feb 1, 2000·92 cites·20 claims
- 4493US5764963AMethod and apparatus for performing maskable multiple color block writesRAMBUS INC·Filed 1995·Granted Jun 9, 1998·104 cites·13 claims
- 4592US7320082B2Power control system for synchronous memory deviceRAMBUS INC·Filed 2003·Granted Jan 15, 2008·36 cites·35 claims
- 4692US5680361AMethod and apparatus for writing to memory componentsRAMBUS INC·Filed 1995·Granted Oct 21, 1997·73 cites·37 claims
- 4791US8458385B2Chip having register to store value that represents adjustment to reference voltageHOROWITZ MARK A·Filed 2012·Granted Jun 4, 2013·8 cites·25 claims
- 4891US8305839B2Memory device having multiple power modesTSERN ELY K·Filed 2012·Granted Nov 6, 2012·9 cites·33 claims
- 4991US6473439B1Method and apparatus for fail-safe resynchronization with minimum latencyRAMBUS INC·Filed 1998·Granted Oct 29, 2002·140 cites·22 claims
- 5091US5872996AMethod and apparatus for transmitting memory requests by transmitting portions of count data in adjacent words of a packetRAMBUS INC·Filed 1997·Granted Feb 16, 1999·135 cites·5 claims
Showing the top 50 of 134 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →