Inventor · disambiguated record
Riccardo Gemelli
Also filed as: GEMELLI RICCARDO · GEMELLI RICCARDO GIORGIO
17 granted patents·2 pending applications·271 citations·filing 1999–2022
93Inventor score
Files withITALTEL SPA7ST MICROELECTRONICS INT NV3CUCCHI SILVIO2NOKIA SOLUTIONS & NETWORKS OY2ST MICROELECTRONICS GRENOBLE 22
Top patents by PatentIndex Score
19 records- 0192US9154446B2Device and method for switching data traffic in a digital transmission networkGEMELLI RICCARDO·Filed 2011·Granted Oct 6, 2015·81 cites·10 claims
- 0291US7130942B2Interface bus protocol for managing transactions in a system of distributed microprocessor interfaces toward marco-cell based designs implemented as ASIC or FPGA bread boardingITALTEL SPA·Filed 2005·Granted Oct 31, 2006·36 cites·15 claims
- 0389US6970966B2System of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative common bus protocolITALTEL SPA·Filed 2002·Granted Nov 29, 2005·65 cites·36 claims
- 0481US8594136B2Transmission of parallel data flows on a parallel busCUCCHI SILVIO·Filed 2009·Granted Nov 26, 2013·12 cites·13 claims
- 0578US11055173B2Redundant storage of error correction code (ECC) checkbits for validating proper operation of a static random access memory (SRAM)ST MICROELECTRONICS GRENOBLE 2·Filed 2019·Granted Jul 6, 2021·2 cites·21 claims
- 0675US7082563B2Automated method for generating the cyclic redundancy check for transmission of multi-protocol packetsITALTEL SPA·Filed 2003·Granted Jul 25, 2006·34 cites·6 claims
- 0767US7289502B1Method and device for routing or compressing packets destination address containing classless addressITALTEL SPA·Filed 2000·Granted Oct 30, 2007·17 cites·24 claims
- 0862US9203725B2Update of a cumulative residence time of a packet in a packet-switched communication networkRONCHETTI LUIGI·Filed 2011·Granted Dec 1, 2015·3 cites·15 claims
- 0955US10379937B2Memory architecture including response manager for error correction circuitST MICROELECTRONICS INT NV·Filed 2017·Granted Aug 13, 2019·0 cites·23 claims
- 1054US10860415B2Memory architecture including response manager for error correction circuitST MICROELECTRONICS INT NV·Filed 2019·Granted Dec 8, 2020·0 cites·18 claims
- 1154US10528422B2Redundant storage of error correction code (ECC) checkbits for validating proper operation of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2017·Granted Jan 7, 2020·0 cites·23 claims
- 1253US6964574B2Daughter board for a prototyping systemITALTEL SPA·Filed 2001·Granted Nov 15, 2005·8 cites·16 claims
- 1351US11463720B2Functional safety method, system, and corresponding computer program productST MICROELECTRONICS SRL·Filed 2018·Granted Oct 4, 2022·0 cites·20 claims
- 1451US7036095B2Clock generation system for a prototyping apparatusITALTEL SPA·Filed 2002·Granted Apr 25, 2006·5 cites·2 claims
- 1548US8429511B2Equipment protection method and apparatusCUCCHI SILVIO·Filed 2009·Granted Apr 23, 2013·0 cites·15 claims
- 1644US11436162B2Functional safety method, corresponding system-on-chip, device and vehicleST MICROELECTRONICS GRENOBLE 2·Filed 2020·Granted Sep 6, 2022·0 cites·20 claims
- 1744US2025293920A1Alarm managementNOKIA SOLUTIONS & NETWORKS OY·Filed 2022·Application pending·0 cites
- 1841US2024098566A1Load management of overlapping cells based on user throughputNOKIA SOLUTIONS & NETWORKS OY·Filed 2021·Application pending·0 cites
- 1934US6549536B1Method of address compression for cell-based and packet-based protocols and hardware implementations thereofITALTEL SPA·Filed 1999·Granted Apr 15, 2003·8 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →