Inventor · disambiguated record
Richard James Shannon
Also filed as: SHANNON RICHARD · SHANNON RICHARD JAMES
6 granted patents·2 pending applications·7 citations·filing 2017–2024
72Inventor score
Technology areasG06F
Top patents by PatentIndex Score
8 records- 0188US12007896B2Apparatuses, systems, and methods for configuring combined private and shared cache levels in a processor-based systemAMPERE COMPUTING LLC·Filed 2022·Granted Jun 11, 2024·3 cites·17 claims
- 0281US11947454B2Apparatuses, systems, and methods for controlling cache allocations in a configurable combined private and shared cache in a processor-based systemAMPERE COMPUTING LLC·Filed 2022·Granted Apr 2, 2024·1 cites·20 claims
- 0381US11880306B2Apparatus, system, and method for configuring a configurable combined private and shared cacheAMPERE COMPUTING LLC·Filed 2022·Granted Jan 23, 2024·1 cites·14 claims
- 0473US10824529B2Functional safety system error injection technologyINTEL CORP·Filed 2017·Granted Nov 3, 2020·2 cites·22 claims
- 0569US12385975B1Integrated circuits including error protection of fields in transferred information and field-based error signals and related methodsAMPERE COMPUTING LLC·Filed 2024·Granted Aug 12, 2025·0 cites·31 claims
- 0655US12493552B1Performing snoop filter replacement based on history-augmented victimization priority values of snoop filter entries in processor-based devicesAMPERE COMPUTING LLC·Filed 2024·Granted Dec 9, 2025·0 cites·30 claims
- 0749US2025291733A1Multi-core processors evicting cache lines from lower-level caches to higher-level caches by core-to-core transfersAMPERE COMPUTING LLC·Filed 2024·Application pending·0 cites
- 0848US2025245156A1Cache memory system employing a multiple-level hierarchy cache coherency architectureAMPERE COMPUTING LLC·Filed 2024·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →