Inventor · disambiguated record
Rodrigo Alvarez-Icaza Rivera
Also filed as: ALVAREZ-ICAZA RIVERA RODRIGO
36 granted patents·209 citations·filing 2012–2019
97Inventor score
Top patents by PatentIndex Score
36 records- 0196US9466022B2Hardware architecture for simulating a neural network of neuronsIBM·Filed 2015·Granted Oct 11, 2016·21 cites·20 claims
- 0295US9244124B2Initializing and testing integrated circuits with selectable scan chains with exclusive-or outputsIBM·Filed 2014·Granted Jan 26, 2016·12 cites·20 claims
- 0394US8990130B2Consolidating multiple neurosynaptic cores into one memoryIBM·Filed 2012·Granted Mar 24, 2015·42 cites·25 claims
- 0493US9160617B2Faulty core recovery mechanisms for a three-dimensional network on a processor arrayIBM·Filed 2012·Granted Oct 13, 2015·16 cites·25 claims
- 0591US9992057B2Yield tolerance in a neurosynaptic systemIBM·Filed 2014·Granted Jun 5, 2018·12 cites·20 claims
- 0686US10454759B2Yield tolerance in a neurosynaptic systemIBM·Filed 2018·Granted Oct 22, 2019·3 cites·18 claims
- 0786US9940302B2Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor arrayIBM·Filed 2016·Granted Apr 10, 2018·4 cites·20 claims
- 0886US8990616B2Final faulty core recovery mechanisms for a two-dimensional network on a processor arrayIBM·Filed 2012·Granted Mar 24, 2015·9 cites·25 claims
- 0985US9588937B2Array of processor core circuits with reversible tiersIBM·Filed 2013·Granted Mar 7, 2017·7 cites·20 claims
- 1085US9053429B2Mapping neural dynamics of a neural model on to a coarsely grained look-up tableIBM·Filed 2012·Granted Jun 9, 2015·12 cites·22 claims
- 1184US9852006B2Consolidating multiple neurosynaptic core circuits into one reconfigurable memory block maintaining neuronal information for the core circuitsIBM·Filed 2014·Granted Dec 26, 2017·15 cites·20 claims
- 1284US9087301B2Hardware architecture for simulating a neural network of neuronsIBM·Filed 2012·Granted Jul 21, 2015·11 cites·27 claims
- 1381US10282658B2Hardware architecture for simulating a neural network of neuronsIBM·Filed 2016·Granted May 7, 2019·3 cites·15 claims
- 1480US9563841B2Globally asynchronous and locally synchronous (GALS) neuromorphic networkALVAREZ-ICAZA RIVERA RODRIGO·Filed 2012·Granted Feb 7, 2017·12 cites·20 claims
- 1579US9747545B2Self-timed, event-driven neurosynaptic core controllerIBM·Filed 2014·Granted Aug 29, 2017·9 cites·18 claims
- 1675US9424284B2Mapping neural dynamics of a neural model on to a coarsely grained look-up tableIBM·Filed 2015·Granted Aug 23, 2016·2 cites·17 claims
- 1773US10713561B2Multiplexing physical neurons to optimize power and areaIBM·Filed 2015·Granted Jul 14, 2020·2 cites·18 claims
- 1872US10410109B2Peripheral device interconnections for neurosynaptic systemsIBM·Filed 2014·Granted Sep 10, 2019·5 cites·20 claims
- 1970US9886662B2Converting spike event data to digital numeric dataIBM·Filed 2014·Granted Feb 6, 2018·4 cites·20 claims
- 2068US10769519B2Converting digital numeric data to spike event dataIBM·Filed 2017·Granted Sep 8, 2020·1 cites·20 claims
- 2166US10102474B2Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural networkIBM·Filed 2014·Granted Oct 16, 2018·3 cites·20 claims
- 2263US9881252B2Converting digital numeric data to spike event dataIBM·Filed 2014·Granted Jan 30, 2018·2 cites·20 claims
- 2362US11184221B2Yield tolerance in a neurosynaptic systemIBM·Filed 2019·Granted Nov 23, 2021·0 cites·20 claims
- 2460US10650301B2Utilizing a distributed and parallel set of neurosynaptic core circuits for neuronal computation and non-neuronal computationIBM·Filed 2014·Granted May 12, 2020·2 cites·16 claims
- 2559US11341401B2Hardware architecture for simulating a neural network of neuronsIBM·Filed 2019·Granted May 24, 2022·0 cites·12 claims
- 2659US10984307B2Peripheral device interconnections for neurosynaptic systemsIBM·Filed 2019·Granted Apr 20, 2021·0 cites·12 claims
- 2758US10839287B1Globally asynchronous and locally synchronous (GALS) neuromorphic networkIBM·Filed 2018·Granted Nov 17, 2020·0 cites·18 claims
- 2857US9797946B2Initializing and testing integrated circuits with selectable scan chains with exclusive-OR outputsIBM·Filed 2015·Granted Oct 24, 2017·0 cites·18 claims
- 2955US11049001B2Event-based neural network with hierarchical addressing for routing event packets between core circuits of the neural networkIBM·Filed 2018·Granted Jun 29, 2021·0 cites·15 claims
- 3055US10176063B2Faulty core recovery mechanisms for a three-dimensional network on a processor arrayIBM·Filed 2016·Granted Jan 8, 2019·0 cites·20 claims
- 3155US9792251B2Array of processor core circuits with reversible tiersIBM·Filed 2017·Granted Oct 17, 2017·0 cites·20 claims
- 3255US9368489B1Interconnect circuits at three-dimensional (3-D) bonding interfaces of a processor arrayIBM·Filed 2013·Granted Jun 14, 2016·0 cites·20 claims
- 3355US9363137B1Faulty core recovery mechanisms for a three-dimensional network on a processor arrayIBM·Filed 2015·Granted Jun 7, 2016·0 cites·20 claims
- 3454US10755165B2Converting spike event data to digital numeric dataIBM·Filed 2017·Granted Aug 25, 2020·0 cites·15 claims
- 3554US10204118B2Mapping neural dynamics of a neural model on to a coarsely grained look-up tableIBM·Filed 2016·Granted Feb 12, 2019·0 cites·15 claims
- 3654US10169700B2Neuromorphic network comprising asynchronous routers and synchronous core circuitsIBM·Filed 2016·Granted Jan 1, 2019·0 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →