Inventor · disambiguated record
Robert S. Chappell
Also filed as: CHAPPELL ROBERT · CHAPPELL ROBERT S · CHAPPELL ROBERT SOMMER
39 granted patents·11 pending applications·163 citations·filing 2009–2024
96Inventor score
Files withINTEL CORP33CHAPPELL ROBERT S2DIXON MARTIN G2MICROSOFT TECHNOLOGY LICENSING LLC2RAJWAR RAVI2
Top patents by PatentIndex Score
50 records- 0194US8838935B2Apparatus, method, and system for implementing micro page tablesHINTON GLENN·Filed 2010·Granted Sep 16, 2014·79 cites·25 claims
- 0292US12236243B2Apparatuses and methods for speculative execution side channel mitigationINTEL CORP·Filed 2023·Granted Feb 25, 2025·2 cites·28 claims
- 0392US10282296B2Zeroing a cache lineINTEL CORP·Filed 2016·Granted May 7, 2019·7 cites·22 claims
- 0490US10409612B2Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative executionINTEL CORP·Filed 2015·Granted Sep 10, 2019·7 cites·20 claims
- 0588US11635965B2Apparatuses and methods for speculative execution side channel mitigationINTEL CORP·Filed 2018·Granted Apr 25, 2023·5 cites·24 claims
- 0684US9740484B2Processor-based apparatus and method for processing bit streams using bit-oriented instructions through byte-oriented storageGOPAL VINODH·Filed 2011·Granted Aug 22, 2017·8 cites·12 claims
- 0783US11126438B2System, apparatus and method for a hybrid reservation station for a processorINTEL CORP·Filed 2019·Granted Sep 21, 2021·4 cites·17 claims
- 0882US11294809B2Apparatuses and methods for a processor architectureINTEL CORP·Filed 2018·Granted Apr 5, 2022·2 cites·7 claims
- 0981US9619750B2Method and apparatus for store dependence predictionINTEL CORP·Filed 2013·Granted Apr 11, 2017·7 cites·10 claims
- 1081US9244827B2Store address prediction for memory disambiguation in a processing deviceKIM HO-SEOP·Filed 2013·Granted Jan 26, 2016·7 cites·24 claims
- 1181US9069690B2Concurrent page table walker control for TLB miss handlingHILDESHEIM GUR·Filed 2012·Granted Jun 30, 2015·9 cites·19 claims
- 1279US2025053651A1Microarchitectural mechanisms for the prevention of side-channel attacks using a thread identification (tid) and a privilege level bitINTEL CORP·Filed 2024·Application pending·0 cites
- 1377US9524263B2Method and apparatus for bus lock assistanceCHAPPELL ROBERT S·Filed 2012·Granted Dec 20, 2016·5 cites·23 claims
- 1477US9298632B2Hybrid cache state and filter tracking of memory operations during a transactionCHAPPELL ROBERT S·Filed 2012·Granted Mar 29, 2016·6 cites·20 claims
- 1575US10031847B2System and method for replacement in associative memories using weighted PLRU treesINTEL CORP·Filed 2016·Granted Jul 24, 2018·3 cites·20 claims
- 1675US2024296051A1Apparatuses and methods for speculative execution side channel mitigationINTEL CORP·Filed 2024·Application pending·0 cites
- 1773US12130740B2Apparatuses and methods for a processor architectureINTEL CORP·Filed 2022·Granted Oct 29, 2024·0 cites·15 claims
- 1873US9423959B2Method and apparatus for store durability and ordering in a persistent memory architectureINTEL CORP·Filed 2013·Granted Aug 23, 2016·3 cites·18 claims
- 1972US12130915B2Microarchitectural mechanisms for the prevention of side-channel attacks using a thread identification (TID) and a privilege level bitINTEL CORP·Filed 2022·Granted Oct 29, 2024·0 cites·24 claims
- 2069US10719355B2Criticality based port schedulingINTEL CORP·Filed 2018·Granted Jul 21, 2020·1 cites·20 claims
- 2167US11106599B2System and method for replacement in associative memories using weighted PLRU treesINTEL CORP·Filed 2019·Granted Aug 31, 2021·1 cites·19 claims
- 2266US11615031B2Memory management apparatus and method for managing different page tables for different privilege levelsINTEL CORP·Filed 2021·Granted Mar 28, 2023·0 cites·20 claims
- 2366US8631207B2Cache memory power reduction techniquesFANG ZHEN·Filed 2009·Granted Jan 14, 2014·4 cites·19 claims
- 2464US11238155B2Microarchitectural mechanisms for the prevention of side-channel attacksINTEL CORP·Filed 2019·Granted Feb 1, 2022·0 cites·24 claims
- 2563US10901772B2Virtualization exceptionsINTEL CORP·Filed 2019·Granted Jan 26, 2021·0 cites·10 claims
- 2662US10678712B2Method and apparatus for bus lock assistanceINTEL CORP·Filed 2019·Granted Jun 9, 2020·0 cites·25 claims
- 2760US11144472B2Memory management apparatus and method for managing different page tables for different privilege levelsINTEL CORP·Filed 2019·Granted Oct 12, 2021·0 cites·29 claims
- 2860US10216650B2Method and apparatus for bus lock assistanceINTEL CORP·Filed 2018·Granted Feb 26, 2019·0 cites·25 claims
- 2959US9348766B2Balanced P-LRU tree for a “multiple of 3” number of ways cacheBASEL ADI·Filed 2011·Granted May 24, 2016·2 cites·24 claims
- 3058US9880948B2Method and apparatus for bus lock assistanceINTEL CORP·Filed 2016·Granted Jan 30, 2018·0 cites·25 claims
- 3157US10296366B2Virtualization exceptionsINTEL CORP·Filed 2016·Granted May 21, 2019·0 cites·6 claims
- 3256US12340224B2Systems, methods, and apparatuses to control CPU speculation for the prevention of side-channel attacksINTEL CORP·Filed 2023·Granted Jun 24, 2025·0 cites·7 claims
- 3355US9563455B2Virtualization exceptionsINTEL CORP·Filed 2013·Granted Feb 7, 2017·0 cites·6 claims
- 3454US11675594B2Systems, methods, and apparatuses to control CPU speculation for the prevention of side-channel attacksINTEL CORP·Filed 2018·Granted Jun 13, 2023·0 cites·18 claims
- 3554US10409611B2Apparatus and method for transactional memory and lock elision including abort and end instructions to abort or commit speculative executionINTEL CORP·Filed 2015·Granted Sep 10, 2019·0 cites·20 claims
- 3653US11327754B2Method and apparatus for approximation using polynomialsINTEL CORP·Filed 2019·Granted May 10, 2022·0 cites·20 claims
- 3752US8516577B2Regulating atomic memory operations to prevent denial of service attackBAIR MICHAEL S·Filed 2010·Granted Aug 20, 2013·1 cites·20 claims
- 3850US9558127B2Instruction and logic for a cache prefetcher and dataless fill bufferINTEL CORP·Filed 2014·Granted Jan 31, 2017·0 cites·17 claims
- 3950US2014059333A1Method, apparatus, and system for speculative abort control mechanismsDIXON MARTIN G·Filed 2012·Application pending·0 cites
- 4048US10503662B2Systems, apparatuses, and methods for implementing temporary escalated privilegeDIXON MARTIN G·Filed 2012·Granted Dec 10, 2019·0 cites·12 claims
- 4147US9311241B2Method and apparatus to write modified cache data to a backing store while retaining write permissionsINTEL CORP·Filed 2012·Granted Apr 12, 2016·0 cites·24 claims
- 4247US2021089316A1Deep learning implementations using systolic arrays and fused operationsINTEL CORP·Filed 2019·Application pending·0 cites
- 4347US2024385867A1Dynamic performance monitoring virtualization supportMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Application pending·0 cites
- 4446US2014189192A1Apparatus and method for a multiple page size translation lookaside buffer (tlb)RAIKIN SHLOMO·Filed 2012·Application pending·0 cites
- 4545US2024004680A1CPU Core Off-parkingMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2022·Application pending·0 cites
- 4642US9733939B2Physical reference list for tracking physical register sharingINTEL CORP·Filed 2012·Granted Aug 15, 2017·0 cites·22 claims
- 4742US2015032998A1Method, apparatus, and system for transactional speculation control instructionsRAJWAR RAVI·Filed 2012·Application pending·0 cites
- 4842US2014379996A1Method, apparatus, and system for transactional speculation control instructionsRAJWAR RAVI·Filed 2012·Application pending·0 cites
- 4939US2018004521A1Processors, methods, and systems to identify stores that cause remote transactional execution abortsINTEL CORP·Filed 2016·Application pending·0 cites
- 5035US2014095814A1Memory Renaming Mechanism in MicroarchitectureMARDEN MORRIS·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →