Inventor · disambiguated record
Rohit Galatage
Also filed as: GALATAGE ROHIT · GALATAGE ROHIT V
9 granted patents·14 pending applications·14 citations·filing 2014–2023
79Inventor score
Top patents by PatentIndex Score
23 records- 0195US10141414B1Negative capacitance matching in gate electrode structuresGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 27, 2018·12 cites·18 claims
- 0272US10332969B2Negative capacitance matching in gate electrode structuresGLOBALFOUNDRIES INC·Filed 2018·Granted Jun 25, 2019·1 cites·20 claims
- 0370US10446659B2Negative capacitance integration through a gate contactGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 15, 2019·1 cites·16 claims
- 0454US10629428B2Metal insulator metal capacitor devicesGLOBALFOUNDRIES INC·Filed 2018·Granted Apr 21, 2020·0 cites·14 claims
- 0553US2024204103A1Transistor gate-channel arrangements with multiple dipole materialsINTEL CORP·Filed 2022·Application pending·0 cites
- 0652US9263541B2Alternative gate dielectric films for silicon germanium and germanium channel materialsGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 16, 2016·0 cites·20 claims
- 0752US2025113603A1Gate-all-around integrated circuit structures having depopulated channel structures using split source or drain approachesINTEL CORP·Filed 2023·Application pending·0 cites
- 0851US2023420460A1Lower device access in stacked transistor devicesINTEL CORP·Filed 2022·Application pending·0 cites
- 0950US2023402513A1Source and drain contacts formed using sacrificial regions of source and drainINTEL CORP·Filed 2022·Application pending·0 cites
- 1050US2024204060A1Nanoribbon stacks without dielectric protection caps for top nanoribbonsINTEL CORP·Filed 2022·Application pending·0 cites
- 1149US2023420528A1Self-aligned embedded source and drain contactsINTEL CORP·Filed 2022·Application pending·0 cites
- 1249US2023402507A1Dual metal silicide for stacked transistor devicesINTEL CORP·Filed 2022·Application pending·0 cites
- 1348US2024222521A1Technologies for ribbon field effect transistors with variable fin numbersINTEL CORP·Filed 2022·Application pending·0 cites
- 1448US2023395718A13d source and drain contacts tuned for vertically stacked pmos and nmosINTEL CORP·Filed 2022·Application pending·0 cites
- 1548US2023395697A1Removal of upper channel bodies in stacked gate-all-around (gaa) device structuresINTEL CORP·Filed 2022·Application pending·0 cites
- 1648US2023395717A13d source and drain contacts tuned for pmos and nmosINTEL CORP·Filed 2022·Application pending·0 cites
- 1748US2023420562A1Diffusion cut stressors for stacked transistorsINTEL CORP·Filed 2022·Application pending·0 cites
- 1847US2024222376A1Technologies for ribbon field effect transistors with variable fin channel dimensionsINTEL CORP·Filed 2022·Application pending·0 cites
- 1946US9484449B2Integrated circuits with diffusion barrier layers and processes for preparing integrated circuits including diffusion barrier layersGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 1, 2016·0 cites·13 claims
- 2046US2016133716A1Alternative gate dielectric films for silicon germanium and germanium channel materialsGLOBALFOUNDRIES INC·Filed 2016·Application pending·0 cites
- 2144US11101348B2Nanosheet field effect transistor with spacers between sheetsGLOBALFOUNDRIES US INC·Filed 2018·Granted Aug 24, 2021·0 cites·15 claims
- 2240US10340146B2Reliability caps for high-k dielectric annealsGLOBALFOUNDRIES INC·Filed 2017·Granted Jul 2, 2019·0 cites·16 claims
- 2338US9577042B1Semiconductor structure with multilayer III-V heterostructuresGLOBALFOUNDRIES INC·Filed 2015·Granted Feb 21, 2017·0 cites·9 claims
Join the waitlist — get patent alerts
Get an alert when Rohit Galatage files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →