Inventor · disambiguated record
Rohan U. Mandrekar
Also filed as: MANDREKAR ROHAN · MANDREKAR ROHAN U
25 granted patents·7 pending applications·41 citations·filing 2008–2024
94Inventor score
Top patents by PatentIndex Score
32 records- 0189US8242384B2Through hole-vias in multi-layer printed circuit boardsCASES MOISES·Filed 2009·Granted Aug 14, 2012·13 cites·5 claims
- 0282US8389870B2Coreless multi-layer circuit substrate with minimized pad capacitanceBILLS KEVIN·Filed 2010·Granted Mar 5, 2013·6 cites·2 claims
- 0380US2025015701A1Merged Power DeliveryAPPLE INC·Filed 2024·Application pending·0 cites
- 0478US9600619B2Distribution of power vias in a multi-layer circuit boardIBM·Filed 2015·Granted Mar 21, 2017·2 cites·7 claims
- 0578US9543241B2Interconnect array pattern with a 3:1 signal-to-ground ratioIBM·Filed 2014·Granted Jan 10, 2017·3 cites·14 claims
- 0677US9646925B2Interconnect array pattern with a 3:1 signal-to-ground ratioIBM·Filed 2015·Granted May 9, 2017·2 cites·9 claims
- 0776US11069665B2Trimmable banked capacitorAPPLE INC·Filed 2018·Granted Jul 20, 2021·2 cites·23 claims
- 0876US8658911B2Through-hole-vias in multi-layer printed circuit boardsCASES MOISES·Filed 2012·Granted Feb 25, 2014·3 cites·4 claims
- 0973US12170478B2Merged power deliveryAPPLE INC·Filed 2022·Granted Dec 17, 2024·0 cites·20 claims
- 1070US9232645B2High speed differential wiring in glass ceramic MCMSIBM·Filed 2013·Granted Jan 5, 2016·2 cites·7 claims
- 1170US8766107B2Through-hole-vias in multi-layer printed circuit boardsCASES MOISES·Filed 2012·Granted Jul 1, 2014·1 cites·5 claims
- 1269US9972566B2Interconnect array pattern with a 3:1 signal-to-ground ratioIBM·Filed 2016·Granted May 15, 2018·1 cites·19 claims
- 1369US8619432B2Implementing high-speed signaling via dedicated printed circuit-board mediaBASKA DOUGLAS A·Filed 2010·Granted Dec 31, 2013·2 cites·18 claims
- 1463US10034393B2Implementing high-speed signaling via dedicated printed circuit-board mediaIBM·Filed 2013·Granted Jul 24, 2018·1 cites·11 claims
- 1563US9146735B2Associating workflows with code sections in a document control systemCHUMBLEY ROBERT B·Filed 2009·Granted Sep 29, 2015·3 cites·17 claims
- 1662US11076493B2Implementing high-speed signaling via dedicated printed circuit-board mediaIBM·Filed 2018·Granted Jul 27, 2021·0 cites·10 claims
- 1755US9277653B2Through-hole-vias in multi-layer printed circuit boardsLENOVO ENTPR SOLUTIONS SINGAPORE PTE LTD·Filed 2014·Granted Mar 1, 2016·0 cites·5 claims
- 1854US9456506B2Packaging for eight-socket one-hop SMP topologyIBM·Filed 2013·Granted Sep 27, 2016·0 cites·13 claims
- 1954US9232646B2High speed differential wiring in glass ceramic MCMSIBM·Filed 2013·Granted Jan 5, 2016·0 cites·12 claims
- 2053US9594865B2Distribution of power vias in a multi-layer circuit boardIBM·Filed 2015·Granted Mar 14, 2017·0 cites·13 claims
- 2153US2017006709A1Pad-to-pad embedded capacitance in lieu of signal via transitions in printed circuit boardsIBM·Filed 2015·Application pending·0 cites
- 2252US9773725B2Coreless multi-layer circuit substrate with minimized pad capacitanceIBM·Filed 2015·Granted Sep 26, 2017·0 cites·10 claims
- 2352US2017004923A1Pad-to-pad embedded capacitance in lieu of signal via transitions in printed circuit boardsIBM·Filed 2015·Application pending·0 cites
- 2451US8975525B2Corles multi-layer circuit substrate with minimized pad capacitanceBILLS KEVIN·Filed 2012·Granted Mar 10, 2015·0 cites·3 claims
- 2550US2024088032A1Structure and Method of Fabrication for High Performance Integrated Passive DeviceAPPLE INC·Filed 2022·Application pending·0 cites
- 2649US9445507B2Packaging for eight-socket one-hop SMP topologyIBM·Filed 2015·Granted Sep 13, 2016·0 cites·7 claims
- 2748US9060428B2Coreless multi-layer circuit substrate with minimized pad capacitanceBILLS KEVIN·Filed 2012·Granted Jun 16, 2015·0 cites·2 claims
- 2848US2015170996A1Through-mesh-plane vias in a multi-layered packageIBM·Filed 2013·Application pending·0 cites
- 2943US8257092B2Redundant clock channel for high reliability connectorsCHUN SUNGJUN·Filed 2010·Granted Sep 4, 2012·0 cites·20 claims
- 3041US2010017158A1Generating worst case bit patterns for simultaneous switching noise (ssn) in digital systemsIBM·Filed 2008·Application pending·0 cites
- 3136US2012175763A1Integrated circuit packaging including auxiliary circuitryHARVEY PAUL M·Filed 2011·Application pending·0 cites
- 3232US8593621B2Testing an optical fiber connectionBILLS KEVIN J·Filed 2010·Granted Nov 26, 2013·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →