Inventor · disambiguated record
Robert J. Palermo
Also filed as: PALERMO ROBERT J
9 granted patents·1 pending application·317 citations·filing 1994–2006
91Inventor score
Top patents by PatentIndex Score
10 records- 0177US5765000ADynamic user interrupt scheme in a programmable logic controllerSIEMENS ENERGY & AUTOMAT·Filed 1994·Granted Jun 9, 1998·50 cites·9 claims
- 0271US5724250AMethod and apparatus for performing drive strength adjust optimization in a circuit designUNISYS CORP·Filed 1996·Granted Mar 3, 1998·65 cites·45 claims
- 0370US6760894B1Method and mechanism for performing improved timing analysis on virtual component blocksCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Jul 6, 2004·16 cites·48 claims
- 0467US5831869AMethod of compacting data representations of hierarchical logic designs used for static timing analysisUNISYS CORP·Filed 1995·Granted Nov 3, 1998·67 cites·20 claims
- 0564US6442739B1System and method for timing abstraction of digital logic circuitsCADENCE DESIGN SYSTEMS INC·Filed 1998·Granted Aug 27, 2002·42 cites·33 claims
- 0663US7647220B2Transistor-level timing analysis using embedded simulationCADENCE DESIGN SYSTEMS INC·Filed 2001·Granted Jan 12, 2010·10 cites·36 claims
- 0758US6877143B1System and method for timing abstraction of digital logic circuitsCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Apr 5, 2005·6 cites·21 claims
- 0854US5594917AHigh speed programmable logic controllerSIEMENS ENERGY & AUTOMAT·Filed 1995·Granted Jan 14, 1997·34 cites·12 claims
- 0952US5761097ALogic timing analysis for multiple-clock designsUNISYS CORP·Filed 1996·Granted Jun 2, 1998·27 cites·27 claims
- 1032US2007136600A1Document Verification System and Method of UseWILKINSON JOSEPH N·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →