Inventor · disambiguated record
Ronald D. Rose
Also filed as: ROSE RONALD D · ROSE RONALD DENNIS
27 granted patents·8 pending applications·194 citations·filing 1999–2024
94Inventor score
Top patents by PatentIndex Score
35 records- 0191US7089513B2Integrated circuit design for signal integrity, avoiding well proximity effectsIBM·Filed 2004·Granted Aug 8, 2006·105 cites·20 claims
- 0289US11176308B1Extracting parasitic capacitance from circuit designsIBM·Filed 2020·Granted Nov 16, 2021·3 cites·20 claims
- 0384US9886541B2Process for improving capacitance extraction performanceIBM·Filed 2015·Granted Feb 6, 2018·4 cites·20 claims
- 0482US9985843B2Efficient parallel processing of a network with conflict constraints between nodesIBM·Filed 2015·Granted May 29, 2018·3 cites·20 claims
- 0579US6832361B2System and method for analyzing power distribution using static timing analysisIBM·Filed 2001·Granted Dec 14, 2004·27 cites·34 claims
- 0677US9495218B2Efficient parallel processing of a network with conflict constraints between nodesIBM·Filed 2016·Granted Nov 15, 2016·2 cites·1 claims
- 0776US11314916B2Capacitance extractionIBM·Filed 2020·Granted Apr 26, 2022·1 cites·20 claims
- 0875US10394999B2Analysis of coupled noise for integrated circuit designIBM·Filed 2015·Granted Aug 27, 2019·2 cites·15 claims
- 0969US10685168B2Capacitance extraction for floating metal in integrated circuitIBM·Filed 2018·Granted Jun 16, 2020·1 cites·20 claims
- 1068US8645899B2Method for extracting information for a circuit designWIDIGER DAVID J·Filed 2009·Granted Feb 4, 2014·4 cites·8 claims
- 1168US8612918B2Method for extracting information for a circuit designWIDIGER DAVID J·Filed 2012·Granted Dec 17, 2013·2 cites·17 claims
- 1265US7913216B2Accurate parasitics estimation for hierarchical customized VLSI designIBM·Filed 2008·Granted Mar 22, 2011·3 cites·10 claims
- 1361US11120193B2Analysis of coupled noise for integrated circuit designIBM·Filed 2019·Granted Sep 14, 2021·0 cites·19 claims
- 1457US8655634B2Modeling loading effects of a transistor networkHATHAWAY DAVID J·Filed 2010·Granted Feb 18, 2014·1 cites·17 claims
- 1557US6567773B1Use of static noise analysis for integrated circuits fabricated in a silicon-on-insulator process technologyIBM·Filed 1999·Granted May 20, 2003·35 cites·24 claims
- 1656US9245084B2Virtual sub-net based routingIBM·Filed 2014·Granted Jan 26, 2016·0 cites·7 claims
- 1756US8640062B2Rapid estimation of temperature rise in wires due to Joule heatingAGARWAL KANAK B·Filed 2011·Granted Jan 28, 2014·1 cites·19 claims
- 1855US9853866B2Efficient parallel processing of a network with conflict constraints between nodesIBM·Filed 2017·Granted Dec 26, 2017·0 cites·1 claims
- 1955US9608868B2Efficient parallel processing of a network with conflict constraints between nodesIBM·Filed 2016·Granted Mar 28, 2017·0 cites·1 claims
- 2055US9418190B2Virtual sub-net based routingIBM·Filed 2014·Granted Aug 16, 2016·0 cites·13 claims
- 2155US2025245413A1Timing-aware fillIBM·Filed 2024·Application pending·0 cites
- 2254US2025245411A1Wiring pattern-based parasitic capacitance extractionIBM·Filed 2024·Application pending·0 cites
- 2354US2011088008A1Method for conversion of commercial microprocessor to radiation-hardened processor and resulting processorIBM·Filed 2009·Application pending·0 cites
- 2454US2025156622A1Process of fitting function parameters that facilitates accurate pattern-based 3d capacitance extractionIBM·Filed 2023·Application pending·0 cites
- 2553US10354041B2Process for improving capacitance extraction performanceIBM·Filed 2017·Granted Jul 16, 2019·0 cites·1 claims
- 2653US9646125B2Method for conversion of commercial microprocessor to radiation-hardened processor and resulting processorIBM·Filed 2014·Granted May 9, 2017·0 cites·14 claims
- 2753US2025190662A1Translation of integrated circuit design data into a production formatIBM·Filed 2023·Application pending·0 cites
- 2853US2018121595A1Applying random nets credit in an efficient static timing analysisIBM·Filed 2017·Application pending·0 cites
- 2950US10929581B2Selectively grounding fill wiresIBM·Filed 2019·Granted Feb 23, 2021·0 cites·20 claims
- 3050US9836571B2Applying random nets credit in an efficient static timing analysisIBM·Filed 2015·Granted Dec 5, 2017·0 cites·15 claims
- 3148US8539428B2Method for extracting information for a circuit designWIDIGER DAVID J·Filed 2012·Granted Sep 17, 2013·0 cites·15 claims
- 3245US10169516B2Methods and computer program products for via capacitance extractionIBM·Filed 2015·Granted Jan 1, 2019·0 cites·20 claims
- 3344US7127689B2Method for preventing circuit failures due to gate oxide leakageIBM·Filed 2004·Granted Oct 24, 2006·0 cites·20 claims
- 3440US2003188267A1Circuit and method for modeling I/OIBM·Filed 2002·Application pending·0 cites
- 3537US2017177776A1Partitioning of wiring for capacitance extraction without loss in accuracyIBM·Filed 2015·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Ronald D. Rose files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →