Method for conversion of commercial microprocessor to radiation-hardened processor and resulting processor

Abstract

A method is provided to convert commercial microprocessors to radiation-hardened processors and, more particularly, a method is provided to modify a commercial microprocessor for radiation hardened applications with minimal changes to the technology, design, device, and process base so as to facilitate a rapid transition for such radiation hardened applications. The method is implemented in a computing infrastructure and includes evaluating a probability that one or more components of an existing commercial design will be affected by a single event upset (SEU). The method further includes replacing the one or more components with a component immune to the SEU to create a final device.

1 . A method implemented in a computing infrastructure, comprising:
 evaluating a probability that one or more components of an existing commercial design will be affected by a single event upset (SEU); and   replacing the one or more components with a component immune to the SEU to create a final device.   
     
     
         2 . The method of  claim 1 , wherein:
 sensitive areas of logic of the existing commercial design are rendered immune to the SEU by substituting logic gates containing at least one stacked device;   all digital logic of the existing commercial design are rendered immune to the SEU by substituting logic gates containing by least one stacked field effect transistor (FET) device; and   SRAM and DRAM arrays are rendered immune to the SEU by use of Error Correction Code (ECC) in peripheral logic of the arrays.   
     
     
         3 . The method of  claim 1 , further comprising selecting a reliability grade, representing a desired immunity to an ionizing radiation event. 
     
     
         4 . The method of  claim 3 , wherein the reliability grade takes into account different factors including at least one of cost, efficiency and size of the final design. 
     
     
         5 . The method of  claim 3 , wherein the reliability grade takes into account different factors including at least one of: failure over a predetermined time period; failure rate to a specific flux; reliability of the final design; cost of the final design; size of the final design; and probability of failure at certain energy levels. 
     
     
         6 . The method of  claim 1 , further comprising using an Error Correction Code (ECC) scheme for a DRAM or SRAM to improve robustness of a memory array, wherein the ECC scheme includes physical locations of each bit scattered along an array segment and within a plurality of array segments. 
     
     
         7 . The method of  claim 1 , wherein the replacement includes providing immunity to the final device in logic portions by substituting every logic gate in all or part of the existing commercial design with a functionally equivalent gate composed of SEU-immune devices. 
     
     
         8 . The method of  claim 1 , wherein the final design includes at least one of: a triple modular redundancy, a substitution of every transistor by a stacked device for complementary CMOS gates in SOI technologies which are resistant to latch up; a substitution of every latch with a DICE latch; a substitution of only sensitive latches with an equivalent latch having at least one stacked device in SOI technologies which are resistant to latch up. 
     
     
         9 . The method of  claim 1 , further comprising selecting a process enhancement to provide an immune device. 
     
     
         10 . The method of  claim 9 , wherein the process enhancement includes a silicon-rich-oxide (SRO) film. 
     
     
         11 . A method, comprising:
 evaluating a currently available design using modeling and/or simulation techniques to determine whether pulse spikes cause latch ups;   flattening the design to a transistor-level and organizing it into channel-connected-components (CCCs);   applying a variety of Single Event Transients (SETs) to each CCC resulting in a noise pulse at an output of the each CCC;   using a signal-integrity analysis tool implemented in a computing infrastructure to propagate a resulting noise pulse through logic and to each of the latches;   evaluating a width of the noise pulse at an input of each of the latches;   evaluating a probability of capture by clock edge and applying a logical masking factor;   determining a probability of a logic failure based on a likelihood of a soft error propagating to and switching each of the latches; and   replacing each of the latches having an estimated logic failure rate greater than a target percentage.   
     
     
         12 . The method of  claim 11 , where the signal-integrity analysis tool is improved with current-source models for the CCC. 
     
     
         13 . The method of  claim 12 , further comprising accumulating results for each known source to obtain a failure estimate for each of the latches. 
     
     
         14 . The method of  claim 11 , wherein the replacement of each of the latches is in non-array portions of an input design. 
     
     
         15 . The method of  claim 11 , wherein the evaluation of the currently available design are repeated to evaluate charged particles from each known source. 
     
     
         16 . The method of  claim 15 , wherein each known source includes at least one of: fragments from neutron interactions; alpha particles; wafer materials background; solder bumps; and packaging. 
     
     
         17 . The method of  claim 11 , wherein the modeling and/or simulation techniques include at least one of: charge-collection modeling, bipolar modeling, and circuit simulation to estimate amplitudes of Single Event Transients (SETs). 
     
     
         18 . The method of  claim 17 , wherein the modeling and/or simulation techniques determine a narrow pulse created by charge collected in combinational logic and captured by a clock edge, and frequency of occurrence of the SETs. 
     
     
         19 . The method of  claim 11 , wherein the replacement of each of the latches in non-array portions of the input design is based on a reliability grade. 
     
     
         20 . The method of  claim 19 , wherein:
 for a high reliability grade, every device is replaced by a stacked device; and   for a lower reliability grade, only latches having a likelihood of failure >x % are replaced with a functionally equivalent latch having stacked devices or a DICE latch.   
     
     
         21 . A method comprising:
 obtaining an existing microprocessor design;   targeting a low-power process in the existing microprocessor design; and   performing a physical-design (PD) step with robust power distribution to provide immunity to neutron bursts, wherein the robust power distribution includes at least one of:
 providing immunity to SEUs in logic portions of the microprocessor design; and 
 providing immunity to SEUs in memory portions of the microprocessor design. 
   
     
     
         22 . The method of  claim 21 , wherein:
 providing immunity to SEUs in logic portions of the microprocessor design includes identifying key devices and substituting them with an SEU-immune stacked device in SOI technologies which are resistant to latch up or by substituting every logic gate in the all or part of the design with a functionally equivalent gate composed of SEU-immune stacked devices in SOI technologies which are resistant to latch up; and   providing immunity to SEUs in memory portions of the microprocessor design includes using an error correcting code (ECC) scheme to reduce sensitivity to failure of adjacent FETs in peripheral logic of the arrays.   
     
     
         23 . A memory array comprising a multiple segment memory system which is protected by an ECC scheme used as a replacement for a memory device, wherein the multiple segment memory system transfers an ECC word to and from separate memory segments on global data lines, wherein bits of an ECC word are scattered among multiple wordlines, the wordlines being located in separate memory segments such that physical locations of each ECC bit are separated thereby protecting the memory array from radiation induced errors. 
     
     
         24 . The memory array of  claim 23 , wherein a SEU will affect no more than 1 bit within the ECC word. 
     
     
         25 . The memory array of  claim 23 , wherein each bit is located on a separate wordline in each of the separate memory banks.