Inventor · disambiguated record
Roland Ruehl
Also filed as: RUEHL ROLAND
29 granted patents·541 citations·filing 2005–2021
97Inventor score
Top patents by PatentIndex Score
29 records- 0196US8473874B1Method and apparatus for automatically fixing double patterning loop violationsSHARMA KARUN·Filed 2011·Granted Jun 25, 2013·37 cites·22 claims
- 0295US9904756B1Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with lateral fills in electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Feb 27, 2018·26 cites·20 claims
- 0395US9659138B1Methods, systems, and computer program product for a bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic techniquesCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted May 23, 2017·18 cites·20 claims
- 0495US9652579B1Methods, systems, and computer program product for implementing DRC clean multi-patterning process nodes with parallel fills in electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted May 16, 2017·25 cites·20 claims
- 0595US8516404B1Methods, systems, and articles of manufacture for implementing constraint checking windows for an electronic design for multiple-patterning lithography processesCAO MIN·Filed 2011·Granted Aug 20, 2013·15 cites·30 claims
- 0694US10515177B1Method, system, and computer program product for implementing routing aware placement or floor planning for an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Dec 24, 2019·20 cites·20 claims
- 0794US9396301B1Method, system, and computer program product for interconnecting circuit components with track patterns for electronic circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Jul 19, 2016·27 cites·20 claims
- 0893US7409656B1Method and system for parallelizing computing operationsCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Aug 5, 2008·37 cites·23 claims
- 0992US8807948B2System and method for automated real-time design checkingLUO WILBUR·Filed 2011·Granted Aug 19, 2014·81 cites·39 claims
- 1092US7689948B1System and method for model-based scoring and yield predictionCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Mar 30, 2010·35 cites·20 claims
- 1191US9117052B1Methods, systems, and articles of manufacture for interactively implementing physical electronic designs with track patternsCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Aug 25, 2015·15 cites·22 claims
- 1291US8739095B2Method, system, and program product for interactive checking for double pattern lithography violationsCAO MIN·Filed 2010·Granted May 27, 2014·20 cites·27 claims
- 1391US7725845B1System and method for layout optimization using model-based verificationCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted May 25, 2010·26 cites·20 claims
- 1490US11842130B1Model-based simulation result predictor for circuit designCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Dec 12, 2023·4 cites·20 claims
- 1590US9372955B1Method, system, and computer program product for implementing repetitive track patterns for electronic circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Jun 21, 2016·15 cites·20 claims
- 1690US7707528B1System and method for performing verification based upon both rules and modelsCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Apr 27, 2010·25 cites·23 claims
- 1789US10049175B1Methods, systems, and articles of manufacture for interactively implementing physical electronic designs with track patternsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Aug 14, 2018·6 cites·20 claims
- 1886US9064063B1Methods, systems, and articles of manufacture for implementing interactive, real-time checking or verification of complex constraintsYU HENRY·Filed 2012·Granted Jun 23, 2015·13 cites·31 claims
- 1984US8645902B1Methods, systems, and computer program products for implementing interactive coloring of physical design components in a physical electronic design with multiple-patterning techniques awarenessYU HENRY·Filed 2012·Granted Feb 4, 2014·8 cites·37 claims
- 2083US7657856B1Method and system for parallel processing of IC design layoutsCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Feb 2, 2010·15 cites·28 claims
- 2182US10346573B1Method and system for performing incremental post layout simulation with layout editsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Jul 9, 2019·5 cites·20 claims
- 2282US7904852B1Method and system for implementing parallel processing of electronic design automation toolsCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Mar 8, 2011·20 cites·60 claims
- 2380US9164969B1Method and system for implementing a stream reader for EDA toolsGUMASTE UDAYAN ANAND·Filed 2009·Granted Oct 20, 2015·16 cites·30 claims
- 2480US7886243B1System and method for using rules-based analysis to enhance models-based analysisCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Feb 8, 2011·12 cites·13 claims
- 2575US10296695B1Method, system, and computer program product for implementing track patterns for electronic circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted May 21, 2019·4 cites·20 claims
- 2674US10635770B1Methods, systems, and computer program products for implementing an electronic design with hybrid analysis techniquesCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Apr 28, 2020·2 cites·20 claims
- 2774US8694943B1Methods, systems, and computer program product for implementing electronic designs with connectivity and constraint awarenessYU HENRY·Filed 2012·Granted Apr 8, 2014·4 cites·42 claims
- 2869US7984399B1System and method for random defect yield simulation of chip with built-in redundancyCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Jul 19, 2011·5 cites·16 claims
- 2965US8448096B1Method and system for parallel processing of IC design layoutsWANG XIAOJUN·Filed 2006·Granted May 21, 2013·5 cites·22 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →