Inventor · disambiguated record
Ross Segelken
Also filed as: SEGELKEN ROSS · SEGELKEN ROSS A · SEGELKEN ROSS ANDREW
19 granted patents·5 pending applications·286 citations·filing 2002–2024
93Inventor score
Top patents by PatentIndex Score
24 records- 0196US6735682B2Apparatus and method for address calculationINTEL CORP·Filed 2002·Granted May 11, 2004·193 cites·21 claims
- 0292US10642744B2Memory type which is cacheable yet inaccessible by speculative instructionsNVIDIA CORP·Filed 2018·Granted May 5, 2020·21 cites·24 claims
- 0390US9875105B2Checkpointed buffer for re-entry from runaheadROZAS GUILLERMO J·Filed 2012·Granted Jan 23, 2018·20 cites·18 claims
- 0483US7262621B1Method and apparatus for integrated mixed-signal or analog testingSYNOPSYS INC·Filed 2005·Granted Aug 28, 2007·12 cites·12 claims
- 0580US9632976B2Lazy runahead operation for a microprocessorNVIDIA CORP·Filed 2012·Granted Apr 25, 2017·5 cites·20 claims
- 0675US9563432B2Dynamic configuration of processing pipeline based on determined type of fetched instructionNVIDIA CORP·Filed 2013·Granted Feb 7, 2017·6 cites·16 claims
- 0773US9396117B2Instruction cache power reductionAGGARWAL ANEESH·Filed 2012·Granted Jul 19, 2016·5 cites·21 claims
- 0870US7047397B2Method and apparatus to execute an instruction with a semi-fast operation in a staggered ALUINTEL CORP·Filed 2002·Granted May 16, 2006·14 cites·13 claims
- 0966US10146545B2Translation address cache for a microprocessorSEGELKEN ROSS·Filed 2012·Granted Dec 4, 2018·3 cites·14 claims
- 1065US10108424B2Profiling code portions to generate translationsNVIDIA CORP·Filed 2013·Granted Oct 23, 2018·2 cites·21 claims
- 1162US12511127B2Dynamic reconfiguration of a multi-core processor to a unified coreNVIDIA CORP·Filed 2024·Granted Dec 30, 2025·0 cites·21 claims
- 1262US9552032B2Branch prediction power reductionAGGARWAL ANEESH·Filed 2012·Granted Jan 24, 2017·2 cites·21 claims
- 1360US10241810B2Instruction-optimizing processor with branch-count table in hardwareBRAUCH RUPERT·Filed 2012·Granted Mar 26, 2019·2 cites·18 claims
- 1456US9891972B2Lazy runahead operation for a microprocessorNVIDIA CORP·Filed 2017·Granted Feb 13, 2018·0 cites·26 claims
- 1555US9880846B2Improving hit rate of code translation redirection table with replacement strategy based on usage history table of evicted entriesTUCK NATHAN·Filed 2012·Granted Jan 30, 2018·1 cites·20 claims
- 1654US10324725B2Fault detection in instruction translationsNVIDIA CORP·Filed 2018·Granted Jun 18, 2019·0 cites·16 claims
- 1751US2025265224A1Dynamic reconfiguration of a unified core processor to a multi-core processorNVIDIA CORP·Filed 2024·Application pending·0 cites
- 1849US2014189310A1Fault detection in instruction translationsNVIDIA CORP·Filed 2012·Application pending·0 cites
- 1948US9823931B2Queued instruction re-dispatch after runaheadNVIDIA CORP·Filed 2012·Granted Nov 21, 2017·0 cites·20 claims
- 2048US9740553B2Managing potentially invalid results during runaheadNVIDIA CORP·Filed 2012·Granted Aug 22, 2017·0 cites·20 claims
- 2148US2006206693A1Method and apparatus to execute an instruction with a semi-fast operation in a staggered ALUSEGELKEN ROSS A·Filed 2006·Application pending·0 cites
- 2243US2004128479A1Method and apparatus for variable length instruction parallel decodingFiled 2002·Application pending·0 cites
- 2342US2014164738A1Instruction categorization for runahead operationNVIDIA CORP·Filed 2012·Application pending·0 cites
- 2441US9547358B2Branch prediction power reductionAGGARWAL ANEESH·Filed 2012·Granted Jan 17, 2017·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →