Fault detection in instruction translations

Abstract

In one embodiment, a method for identifying and replacing code translations that generate spurious fault events includes detecting, while executing a first native translation of target instruction set architecture (ISA) instructions, occurrence of a fault event, executing the target ISA instructions or a functionally equivalent version thereof, determining whether occurrence of the fault event is replicated while executing the target ISA instructions or the functionally equivalent version thereof, and in response to determining that the fault event is not replicated, determining whether to allow future execution of the first native translation or to prevent such future execution in favor of forming and executing one or more alternate native translations.

1 . A method for identifying and replacing code translations that generate spurious fault events, comprising:
 detecting, while executing a first native translation of target instruction set architecture (ISA) instructions, occurrence of a fault event, the first native translation being executable to achieve substantially equivalent functionality as obtainable via execution of the target ISA instructions;   decoding the target ISA instructions into functionally equivalent native instructions with a hardware decoder in response to detecting occurrence of the fault event while executing the first native translation;   executing the target ISA instructions or a functionally equivalent version thereof, where such execution is performed without executing the first native translation;   determining whether occurrence of the fault event is replicated while executing the target ISA instructions or the functionally equivalent version thereof; and   in response to determining that the fault event is not replicated, determining whether to allow future execution of the first native translation or to prevent such future execution in favor of forming and executing one or more alternate native translations.   
     
     
         2 . The method of  claim 1 , where determining whether to allow or prevent future execution of the first native translation includes forming and executing the one or more alternate translations upon determining that a performance cost associated with forming the one or more alternate translations is less than a performance cost associated with continuing to execute the first native translation. 
     
     
         3 . The method of  claim 1 , further comprising incrementing a counter associated with the first native translation, and where determining whether to allow or prevent future execution of the first native translation includes preventing such execution and forming and executing the one or more alternate translations in response to saturating the counter. 
     
     
         4 . The method of  claim 3 , where the counter is incremented in response to determining that a fault event occurring during execution of the first native translation is not replicated when executing target ISA instructions or a functionally equivalent version thereof. 
     
     
         5 . The method of  claim 1 , further comprising forming one or more alternate native translations to be executed instead of the first native translation, where the one or more alternative native translations are optimized differently than the first native translation so as to avoid occurrence of the fault event that was encountered during execution of the first native translation. 
     
     
         6 . The method of  claim 5 , where the one or more alternative native translations include fewer optimizations than employed in the first native translation. 
     
     
         7 . The method of  claim 1 , further comprising:
 pausing execution of the target ISA instructions or the functionally equivalent version thereof responsive to encountering a target of a branch instruction;   determining whether an instruction pointer is within an instruction pointer boundary corresponding to the first native translation when execution is paused; and   if the instruction pointer is beyond the instruction pointer boundary when execution is paused, determining that occurrence of the fault event is not replicated while executing the target ISA instructions or the functionally equivalent version thereof.   
     
     
         8 . The method of  claim 7 , where the target of the branch instruction includes a field having a bit that is set responsive to detecting occurrence of the fault event while executing the first native translation, and execution is paused responsive to encountering the set bit. 
     
     
         9 . The method of  claim 8 , where the microprocessor includes a hardware redirector that is accessed by a hardware decoder to check for a native translation corresponding to a portion of target ISA instructions, and where access to the hardware redirector by the hardware decoder is disabled when executing the target ISA instructions or the functionally equivalent version thereof without executing the first native translation 
     
     
         10 . The method of  claim 1 , further comprising:
 setting a counter for execution of the target ISA instructions or the functionally equivalent version thereof based on the fault event,   pausing execution of the target ISA instructions or the functionally equivalent version thereof responsive to the counter expiring;   determining whether an instruction pointer is within an instruction pointer boundary corresponding to the first native translation when execution is paused; and   if the instruction pointer is beyond the instruction pointer boundary when execution is paused, determining that occurrence of the fault event is not replicated while executing the target ISA instructions or the functionally equivalent version thereof.   
     
     
         11 . A micro-processing and memory system comprising:
 memory configured to store target ISA instructions and a first native translation executable to achieve substantially equivalent functionality as obtainable via execution of the target ISA instructions;   a microprocessor including, execution logic configured to (1) detect, during execution of the first native translation, occurrence of a fault event, (2) roll back execution of the first native translation in response to detecting occurrence of the fault event while executing the first native translation;   a hardware decoder configured to decode the target ISA instructions into functionally equivalent native instructions in response to detecting occurrence of the fault event while executing the first native translation, where the execution logic is configured to execute the target ISA instructions or a functionally equivalent version thereof, where such execution is performed without executing the first native translation; and   a translation manager configured to (1) determine whether occurrence of the fault event is replicated while executing the target ISA instructions or the functionally equivalent version thereof, and (2) in response to determining that the fault event is not replicated, determine whether to allow future execution of the first native translation or to prevent such future execution in favor of forming and executing one or more alternate native translations.   
     
     
         12 . The system of  claim 11 , where determining whether to allow or prevent future execution of the first native translation includes forming and executing the one or more alternate translations upon determining that a performance cost associated with forming the one or more alternate translations is less than a performance cost associated with continuing to execute the first native translation. 
     
     
         13 . The system of  claim 11 , where the execution logic is configured to increment a counter associated with the first native translation, and where determining whether to allow or prevent future execution of the first native translation includes preventing such execution and forming and executing the one or more alternate translations in response to saturating the counter. 
     
     
         14 . The system of  claim 12 , where the translation manager is configured to form one or more alternate native translations to be executed instead of the first native translation, where the one or more alternative native translations are optimized differently than the first native translation so as to avoid occurrence of the fault event that was encountered during execution of the first native translation. 
     
     
         15 . The system of  claim 11 , where the execution logic is configured to pause execution of the target ISA instructions or the functionally equivalent version thereof responsive to encountering a target of a branch instruction, and where the translation manager is configured to (1) determine whether an instruction pointer is within an instruction pointer boundary corresponding to the first native translation when execution is paused, and (2) if the instruction pointer is beyond the instruction pointer boundary when execution is paused, determine that occurrence of the fault event is not replicated while executing the target ISA instructions or the functionally equivalent version thereof. 
     
     
         16 . The system of  claim 15 , where the target of the branch instruction includes a field having a bit that is set responsive to detecting occurrence of the fault event while executing the first native translation, and execution is paused responsive to encountering the set bit 
     
     
         17 . The system of  claim 11 , where the translation manager is configured to set a counter for execution of the target ISA instructions or the functionally equivalent version thereof based on detection of the fault event, where the execution logic is configured to pause execution of the target ISA instructions or the functionally equivalent version thereof responsive to the counter expiring, where the translation manager is configured to determine whether an instruction pointer is within an instruction pointer boundary corresponding to the first native translation when execution is paused, and if the instruction pointer is beyond the instruction pointer boundary when execution is paused, determine that occurrence of the fault event is not replicated while executing the target ISA instructions or the functionally equivalent version thereof. 
     
     
         18 . A method for identifying and replacing code translations that generate spurious fault events, comprising:
 detecting, while executing a first native translation of target instruction set architecture (ISA) instructions, occurrence of a fault event, the first native translation being executable to achieve substantially equivalent functionality as obtainable via execution of the target ISA instructions;   rolling back execution of the first native translation in response to detecting the fault event;   decoding the target ISA instructions into functionally equivalent native instructions with a hardware decoder in response to detecting occurrence of the fault event while executing the first native translation, where targets of branch instructions decoded by the hardware decoder include a field having a bit that is set responsive to encountering the fault event;   executing the native instructions dispatched by the hardware decoder;   pausing execution of the native instructions responsive to encountering a set bit in the field of a target of a branch instruction;   determining whether an instruction pointer is within an instruction pointer boundary corresponding to the first native translation when execution is paused;   if the instruction pointer is beyond the instruction pointer boundary when execution is paused, determining that occurrence of the fault event is not replicated while executing the target ISA instructions or the functionally equivalent version thereof; and   in response to determining that the fault event is not replicated, forming and executing one or more alternate translations upon determining that a performance cost associated with forming the one or more alternate translations is less than a performance cost associated with continuing to execute the first native translation.   
     
     
         19 . The method of  claim 18 , where the one or more alternative native translations are optimized differently than the first native translation so as to avoid occurrence of the fault event that was encountered during execution of the first native translation. 
     
     
         20 . The method of  claim 19 , where the one or more alternative native translations include fewer optimizations than employed in the first native translation.