Inventor · disambiguated record
Robert Walker
Also filed as: WALKER ROBERT · WALKER ROBERT L · WALKER ROBERT LAWRENCE
21 granted patents·1 pending application·1,050 citations·filing 1995–2023
96Inventor score
Top patents by PatentIndex Score
22 records- 0194US6539536B1Electronic design automation system and methods utilizing groups of multiple cells having loop-back connections for modeling port electrical characteristicsSYNOPSYS INC·Filed 2000·Granted Mar 25, 2003·185 cites·20 claims
- 0294US5696771AMethod and apparatus for performing partial unscan and near full scan within design for test applicationsSYNOPSYS INC·Filed 1996·Granted Dec 9, 1997·112 cites·32 claims
- 0393US6106568AHierarchical scan architecture for design for test applicationsSYNOPSYS INC·Filed 1999·Granted Aug 22, 2000·120 cites·20 claims
- 0490US10162918B1Integrated circuit retiming with selective modeling of flip-flop secondary signalsALTERA CORP·Filed 2016·Granted Dec 25, 2018·9 cites·17 claims
- 0590US5703789ATest ready compiler for design for test synthesisSYNOPSYS INC·Filed 1995·Granted Dec 30, 1997·78 cites·36 claims
- 0689US5949692AHierarchical scan architecture for design for test applicationsSYNOPSYS INC·Filed 1996·Granted Sep 7, 1999·89 cites·25 claims
- 0788US10339241B1Methods for incremental circuit design legalization during physical synthesisALTERA CORP·Filed 2016·Granted Jul 2, 2019·6 cites·13 claims
- 0887US5903466AConstraint driven insertion of scan logic for implementing design for test within an integrated circuit designSYNOPSYS INC·Filed 1995·Granted May 11, 1999·162 cites·33 claims
- 0987US5831868ATest ready compiler for design for test synthesisSYNOPSYS INC·Filed 1997·Granted Nov 3, 1998·60 cites·14 claims
- 1085US6067650AMethod and apparatus for performing partial unscan and near full scan within design for test applicationsSYNOPSYS INC·Filed 1997·Granted May 23, 2000·54 cites·16 claims
- 1183US10936772B1Methods for incremental circuit physical synthesisALTERA CORP·Filed 2016·Granted Mar 2, 2021·4 cites·20 claims
- 1279US8266570B2Density-based area recovery in electronic design automationWALKER ROBERT·Filed 2010·Granted Sep 11, 2012·5 cites·21 claims
- 1377US6058252ASystem and method for generating effective layout constraints for a circuit design or the likeSYNOPSYS INC·Filed 1997·Granted May 2, 2000·99 cites·16 claims
- 1472US8527927B2Zone-based area recovery in electronic design automationWALKER ROBERT·Filed 2010·Granted Sep 3, 2013·3 cites·21 claims
- 1571US8621408B2Progressive circuit evaluation for circuit optimizationIYER MAHESH A·Filed 2012·Granted Dec 31, 2013·3 cites·18 claims
- 1668US8578321B2Delta-slack propagation for circuit optimizationIYER MAHESH A·Filed 2012·Granted Nov 5, 2013·2 cites·18 claims
- 1767US5911493AIlluminated umbrellaFiled 1997·Granted Jun 15, 1999·56 cites·11 claims
- 1866US10296701B1Retiming with fixed power-up statesALTERA CORP·Filed 2016·Granted May 21, 2019·1 cites·20 claims
- 1966US8418116B2Zone-based optimization framework for performing timing and design rule optimizationWALKER ROBERT·Filed 2010·Granted Apr 9, 2013·2 cites·20 claims
- 2052US2024330562A1Automated multi-stage design flow based on final quality of resultSYNOPSYS INC·Filed 2023·Application pending·0 cites
- 2144US9189583B2Look-up based buffer tree synthesisSYNOPSYS INC·Filed 2013·Granted Nov 17, 2015·0 cites·18 claims
- 2242US10255404B1Retiming with programmable power-up statesALTERA CORP·Filed 2016·Granted Apr 9, 2019·0 cites·20 claims
Join the waitlist — get patent alerts
Get an alert when Robert Walker files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →