Inventor · disambiguated record
Rubin Ajit Parekhji
Also filed as: PAREKHJI RUBIN · PAREKHJI RUBIN A · PAREKHJI RUBIN AJIT
33 granted patents·2 pending applications·330 citations·filing 2001–2023
97Inventor score
Top patents by PatentIndex Score
35 records- 0197US10591540B2Compressed scan chains with three input mask gates and registersTEXAS INSTRUMENTS INC·Filed 2018·Granted Mar 17, 2020·8 cites·8 claims
- 0296US9952283B2Compressed scan chains with three input mask gates and registersTEXAS INSTRUMENTS INC·Filed 2015·Granted Apr 24, 2018·8 cites·6 claims
- 0396US9229055B2Decompressed scan chain masking circuit shift register with log2(n/n) cellsTEXAS INSTRUMENTS INC·Filed 2015·Granted Jan 5, 2016·8 cites·11 claims
- 0496US9091729B2Scan chain masking qualification circuit shift register and bit-field decodersTEXAS INSTRUMENTS INC·Filed 2014·Granted Jul 28, 2015·13 cites·2 claims
- 0595US11119152B2Functional circuitry, decompressor circuitry, scan circuitry, masking circuitry, qualification circuitryTEXAS INSTRUMENTS INC·Filed 2020·Granted Sep 14, 2021·3 cites·16 claims
- 0695US8887018B2Masking circuit removing unknown bit from cell in scan chainNARAYANAN PRAKASH·Filed 2010·Granted Nov 11, 2014·19 cites·4 claims
- 0794US10746797B1Dynamically protective scan data controlTEXAS INSTRUMENTS INC·Filed 2019·Granted Aug 18, 2020·6 cites·21 claims
- 0892US8671329B2Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processesTEXAS INSTRUMENTS INC·Filed 2013·Granted Mar 11, 2014·17 cites·15 claims
- 0992US8438344B2Low overhead and timing improved architecture for performing error checking and correction for memories and buses in system-on-chips, and other circuits, systems and processesKUMAR SANJAY·Filed 2010·Granted May 7, 2013·19 cites·19 claims
- 1092US8438437B2Structures and control processes for efficient generation of different test clocking sequences, controls and other test signals in scan designs with multiple partitions, and devices, systems and processes of makingJAIN ARVIND·Filed 2010·Granted May 7, 2013·21 cites·46 claims
- 1191US7134061B2At-speed ATPG testing and apparatus for SoC designs having multiple clock domain using a VLCT test platformTEXAS INSTRUMENTS INC·Filed 2003·Granted Nov 7, 2006·69 cites·5 claims
- 1290US11592483B2Compressed scan chain diagnosis by internal chain observation, processes, circuits, devices and systemsTEXAS INSTRUMENTS INC·Filed 2021·Granted Feb 28, 2023·1 cites·11 claims
- 1390US8205125B2Enhanced control in scan tests of integrated circuits with partitioned scan chainsHALES ALAN DAVID·Filed 2009·Granted Jun 19, 2012·40 cites·4 claims
- 1489US8286042B2On-chip seed generation using boolean functions for LFSR re-seeding based logic BIST techniques for low cost field testabilityGANGASANI SWATHI·Filed 2010·Granted Oct 9, 2012·17 cites·13 claims
- 1588US8694276B2Built-in self-test methods, circuits and apparatus for concurrent test of RF modules with a dynamically configurable test structureSONTAKKE ADESH SHARADRAO·Filed 2011·Granted Apr 8, 2014·15 cites·16 claims
- 1687US8799713B2Interruptible non-destructive run-time built-in self-test for field testingGANGASANI SWATHI·Filed 2012·Granted Aug 5, 2014·21 cites·2 claims
- 1784US11921159B2Compressed scan chain diagnosis by internal chain observation, processes, circuits, devices and systemsTEXAS INSTRUMENTS INC·Filed 2023·Granted Mar 5, 2024·0 cites·20 claims
- 1881US11994559B2Tests for integrated circuit (IC) chipsTEXAS INSTRUMENTS INC·Filed 2022·Granted May 28, 2024·1 cites·20 claims
- 1973US8972807B2Integrated circuits capable of generating test mode control signals for scan testsMITTAL RAJESH·Filed 2012·Granted Mar 3, 2015·4 cites·20 claims
- 2071US10180454B2Systems and methods of testing multiple diesTEXAS INSTRUMENTS INC·Filed 2016·Granted Jan 15, 2019·1 cites·28 claims
- 2171US9581645B2Test circuit providing different levels of concurrency among radio coresTEXAS INSTRUMENTS INC·Filed 2014·Granted Feb 28, 2017·2 cites·16 claims
- 2271US6925408B2Mixed-signal core design for concurrent testing of mixed-signal, analog, and digital componentsTEXAS INSTRUMENTS INC·Filed 2003·Granted Aug 2, 2005·19 cites·15 claims
- 2369US10606723B2Systems and methods for optimal trim calibrations in integrated circuitsTEXAS INSTRUMENTS INC·Filed 2015·Granted Mar 31, 2020·2 cites·20 claims
- 2468US11320478B2Methods of testing multiple diesTEXAS INSTRUMENTS INC·Filed 2020·Granted May 3, 2022·0 cites·23 claims
- 2568US8856601B2Scan compression architecture with bypassable scan chains for low test mode powerRAVI SRIVATHS·Filed 2010·Granted Oct 7, 2014·3 cites·7 claims
- 2668US8839063B2Circuits and methods for dynamic allocation of scan test resourcesTEXAS INSTRUMENTS INC·Filed 2013·Granted Sep 16, 2014·2 cites·20 claims
- 2763US10684322B2Systems and methods of testing multiple diesTEXAS INSTRUMENTS INC·Filed 2019·Granted Jun 16, 2020·0 cites·8 claims
- 2859US6697982B2Generating netlist test vectors by stripping references to a pseudo inputTEXAS INSTRUMENTS INC·Filed 2001·Granted Feb 24, 2004·8 cites·2 claims
- 2951US12313681B2Identifying defect sensitive codes for testing devices with input or output codeTEXAS INSTRUMENTS INC·Filed 2019·Granted May 27, 2025·0 cites·28 claims
- 3045US9263147B2Method and apparatus for concurrent test of flash memory coresTEXAS INSTRUMENTS INC·Filed 2014·Granted Feb 16, 2016·1 cites·16 claims
- 3141US2007288797A1Generating scan test vectors for proprietary cores using pseudo pinsTEXAS INSTRUMENTS INC·Filed 2007·Application pending·0 cites
- 3238US7120842B2Mechanism to enhance observability of integrated circuit failures during burn-in testsTEXAS INSTRUMENTS INC·Filed 2003·Granted Oct 10, 2006·2 cites·15 claims
- 3336US7213184B2Testing of modules operating with different characteristics of control signals using scan based techniquesTEXAS INSTRUMENTS INC·Filed 2004·Granted May 1, 2007·0 cites·10 claims
- 3436US7203880B2Generating an abbreviated netlist including pseudopin inputs and output nodesTEXAS INSTRUMENTS INC·Filed 2004·Granted Apr 10, 2007·0 cites·2 claims
- 3535US2016003900A1Self-test methods and systems for digital circuitsTEXAS INSTRUMENTS INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →