Generating scan test vectors for proprietary cores using pseudo pins

Abstract

A method generates test vectors for a customer designed integrated circuit having an embedded vendor circuit. The embedded vendor circuit has a proprietary circuit and a nonproprietary circuit. At least one pseudo input is defined to represent a portion of the nonproprietary circuit to emulate the nonproprietary circuit output. An output node of the embedded vendor circuit to which an input of the customer designed circuit is connectable is identified. A test netlist is created which represents circuitry that produces output states at the output node which would be generated by the embedded vendor circuit thereat. The test netlist includes at least one pseudo input and the output node, without including a full netlist of either the proprietary or nonproprietary circuits, and can be used to generate scan test vectors for the customer designed integrated circuit by the automatic test vector generating software program.

1 - 14 . (canceled)  
   
   
       15 . A process for generating scan test vectors for a customer designed integrated circuit having an embedded vendor circuit, the embedded vendor circuit having a proprietary circuit and a nonproprietary circuit, comprising: 
 A. creating at least one pseudo input to represent at least a portion of the nonproprietary circuit that is not necessary to be exercised by the automatic test vector generating software program to generate test vectors for the customer designed integrated circuit;    B. identifying an output node of the embedded vendor circuit to which an input of the customer designed circuit is connectable;    C. creating a test netlist to represent circuitry producing output states at the output node that would be generated by the embedded vendor circuit thereat, the test netlist including at least one pseudo input and the output node; and    D. generating scan test vectors for the customer designed integrated circuit with automatic test vector generating software program using the test netlist with the output node connected to the input of a netlist representing the customer supplied circuitry.    
   
   
       16 . The process of  claim 15  in which the creating a test list omits creating a full netlist of either the proprietary or nonproprietary circuits.