Inventor · disambiguated record
Russell B. Segal
Also filed as: SEGAL RUSSELL · SEGAL RUSSELL B
22 granted patents·396 citations·filing 1995–2015
96Inventor score
Technology areasG06F
Top patents by PatentIndex Score
22 records- 0188US9189591B2Path-based floorplan analysisSYNOPSYS INC·Filed 2014·Granted Nov 17, 2015·9 cites·13 claims
- 0284US8893073B2Displaying a congestion indicator for a channel in a circuit design layoutSYNOPSYS INC·Filed 2012·Granted Nov 18, 2014·7 cites·15 claims
- 0381US9460258B2Shaping integrated with power network synthesis (PNS) for power grid (PG) alignmentSYNOPSYS INC·Filed 2013·Granted Oct 4, 2016·7 cites·18 claims
- 0478US7114142B1Optimizing locations of pins for blocks in a hierarchical physical design by using physical design information of a prior hierarchical physical designMAGMA DESIGN AUTOMATION INC·Filed 2004·Granted Sep 26, 2006·15 cites·21 claims
- 0574US6496972B1Method and system for circuit design top level and block optimizationSYNOPSYS INC·Filed 1999·Granted Dec 17, 2002·70 cites·28 claims
- 0668US9754070B2Path-based floorplan analysisSYNOPSYS INC·Filed 2015·Granted Sep 5, 2017·1 cites·17 claims
- 0768US5530841AMethod for converting a hardware independent user description of a logic circuit into hardware componentsSYNOPSYS INC·Filed 1995·Granted Jun 25, 1996·32 cites·8 claims
- 0867US6678644B1Integrated circuit models having associated timing exception information therewith for use with electronic design automationSYNOPSYS INC·Filed 1999·Granted Jan 13, 2004·49 cites·21 claims
- 0964US6023568AExtracting accurate and efficient timing models of latch-based designsSYNOPSYS INC·Filed 1996·Granted Feb 8, 2000·44 cites·25 claims
- 1063US9390222B2Determining a set of timing paths for creating a circuit abstractionSYNOPSYS INC·Filed 2014·Granted Jul 12, 2016·1 cites·15 claims
- 1161US6438731B1Integrated circuit models having associated timing exception information therewith for use in circuit design optimizationsSYNOPSYS INC·Filed 1999·Granted Aug 20, 2002·38 cites·31 claims
- 1259US5790830AExtracting accurate and efficient timing models of latch-based designsSYNOPSYS INC·Filed 1995·Granted Aug 4, 1998·36 cites·22 claims
- 1357US5661661AMethod for processing a hardware independent user description to generate logic circuit elements including flip-flops, latches, and three-state buffers and combinations thereofSYNOPSYS INC·Filed 1995·Granted Aug 26, 1997·19 cites·9 claims
- 1453US5748488AMethod for generating a logic circuit from a hardware independent user description using assignment conditionsSYNOPSYS INC·Filed 1995·Granted May 5, 1998·15 cites·14 claims
- 1552US8914759B2Abstract creationSYNOPSYS INC·Filed 2013·Granted Dec 16, 2014·0 cites·12 claims
- 1650US5581781ASynthesizer for generating a logic network using a hardware independent descriptionSYNOPSYS INC·Filed 1995·Granted Dec 3, 1996·13 cites·23 claims
- 1746US6317863B1Method and apparatus for irregular datapath placement in a datapath placement toolSYNOPSYS INC·Filed 1997·Granted Nov 13, 2001·18 cites·14 claims
- 1845US5691911AMethod for pre-processing a hardware independent description of a logic circuitSYNOPSYS INC·Filed 1995·Granted Nov 25, 1997·10 cites·10 claims
- 1944US9026974B2Semiconductor integrated circuit partitioning and timingSYNOPSYS INC·Filed 2013·Granted May 5, 2015·0 cites·18 claims
- 2043US5953235AMethod for processing a hardware independent user description to generate logic circuit elements including flip-flops, latches, and three-state buffers and combinations thereofSYNOPSYS INC·Filed 1997·Granted Sep 14, 1999·8 cites·9 claims
- 2134US5680318ASynthesizer for generating a logic network using a hardware independent descriptionSYNOPSYS INC·Filed 1995·Granted Oct 21, 1997·3 cites·50 claims
- 2231US5737574AMethod for generating a logic circuit from a hardware independent user description using mux conditions and hardware selectorsSYNOPSYS INC·Filed 1995·Granted Apr 7, 1998·1 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →