Inventor · disambiguated record
Rwik Sengupta
Also filed as: SENGUPTA RWIK
43 granted patents·3 pending applications·356 citations·filing 2011–2024
97Inventor score
Files withSAMSUNG ELECTRONICS CO LTD39CADENCE DESIGN SYSTEMS INC3SENGUPTA RWIK2KITTL JORGE A1RODDER MARK S1
Top patents by PatentIndex Score
46 records- 0199US9570395B1Semiconductor device having buried power railSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Feb 14, 2017·94 cites·20 claims
- 0298US9490323B2Nanosheet FETs with stacked nanosheets having smaller horizontal spacing than vertical spacing for large effective widthSAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted Nov 8, 2016·37 cites·18 claims
- 0397US9287357B2Integrated circuits with Si and non-Si nanosheet FET co-integration with low band-to-band tunneling and methods of fabricating the sameSAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted Mar 15, 2016·66 cites·20 claims
- 0496US10886224B2Power distribution network using buried power railSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Jan 5, 2021·17 cites·18 claims
- 0596US9466669B2Multiple channel length finFETs with same physical gate lengthSAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted Oct 11, 2016·16 cites·9 claims
- 0695US9685564B2Gate-all-around field effect transistors with horizontal nanosheet conductive channel structures for MOL/inter-channel spacing and related cell architecturesSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Jun 20, 2017·13 cites·20 claims
- 0794US10811415B2Semiconductor device and method for making the sameSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Oct 20, 2020·10 cites·20 claims
- 0892US10985103B2Apparatus and method of forming backside buried conductor in integrated circuitSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Apr 20, 2021·8 cites·20 claims
- 0992US10566330B2Dielectric separation of partial GAA FETsSAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted Feb 18, 2020·10 cites·20 claims
- 1092US10164121B2Stacked independently contacted field effect transistor having electrically separated first and second gatesSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Dec 25, 2018·8 cites·8 claims
- 1191US9324715B2Flip-flop layout architecture implementation for semiconductor deviceSAMSUNG ELECTRONICS CO LTD·Filed 2014·Granted Apr 26, 2016·16 cites·20 claims
- 1290US11574111B1Electronic design tracing and tamper detection using automatically generated layout patternsCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Feb 7, 2023·3 cites·20 claims
- 1389US9768062B1Method for forming low parasitic capacitance source and drain contactsSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Sep 19, 2017·8 cites·20 claims
- 1487US10910313B2Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitchSAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted Feb 2, 2021·5 cites·12 claims
- 1586US10361195B2Semiconductor device with an isolation gate and method of formingSENGUPTA RWIK·Filed 2015·Granted Jul 23, 2019·7 cites·9 claims
- 1685US11101320B2System and method for efficient enhancement of an on/off ratio of a bitcell based on 3T2R binary weight cell with spin orbit torque MJTs (SOT-MTJs)SAMSUNG ELECTRONICS CO LTD·Filed 2020·Granted Aug 24, 2021·1 cites·19 claims
- 1784US11552067B2Semiconductor cell blocks having non-integer multiple of cell heightsSAMSUNG ELECTRONICS CO LTD·Filed 2020·Granted Jan 10, 2023·2 cites·7 claims
- 1884US11461620B2Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETsSAMSUNG ELECTRONICS CO LTD·Filed 2017·Granted Oct 4, 2022·5 cites·14 claims
- 1984US10026751B2Semiconductor device including a repeater/buffer at higher metal routing layers and methods of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Jul 17, 2018·4 cites·17 claims
- 2080US11189692B2VFET standard cell architecture with improved contact and super viaSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Nov 30, 2021·2 cites·10 claims
- 2180US9443851B2Semiconductor devices including finFETs and local interconnect layers and methods of fabricating the sameSAMSUNG ELECTRONICS CO LTD·Filed 2014·Granted Sep 13, 2016·5 cites·18 claims
- 2278US9659871B2Semiconductor deviceSAMSUNG ELECTRONICS CO LTD·Filed 2014·Granted May 23, 2017·4 cites·10 claims
- 2377US11868698B1Context-aware circuit design layout constructCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Jan 9, 2024·1 cites·20 claims
- 2477US10381315B2Method and system for providing a reverse-engineering resistant hardware embedded security moduleSAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted Aug 13, 2019·2 cites·20 claims
- 2576US10153368B2Unipolar complementary logicSAMSUNG ELECTRONICS CO LTD·Filed 2017·Granted Dec 11, 2018·2 cites·19 claims
- 2676US9490263B2Semiconductor device and method of forming the sameSAMSUNG ELECTRONICS CO LTD·Filed 2014·Granted Nov 8, 2016·6 cites·12 claims
- 2774US10784198B2Power rail for standard cell blockSAMSUNG ELECTRONICS CO LTD·Filed 2017·Granted Sep 22, 2020·2 cites·20 claims
- 2873US2024379653A1Semiconductor cell blocks having non-integer multiple of cell heightsSAMSUNG ELECTRONICS CO LTD·Filed 2024·Application pending·0 cites
- 2972US11727258B2Multi-bit, SoC-compatible neuromorphic weight cell using ferroelectric FETsSAMSUNG ELECTRONICS CO LTD·Filed 2022·Granted Aug 15, 2023·0 cites·18 claims
- 3070US12080703B2Semiconductor cell blocks having non-integer multiple of cell heightsSAMSUNG ELECTRONICS CO LTD·Filed 2022·Granted Sep 3, 2024·0 cites·14 claims
- 3170US10861950B2Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitchSAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted Dec 8, 2020·1 cites·16 claims
- 3265US12046635B2VFET standard cell architecture with improved contact and super viaSAMSUNG ELECTRONICS CO LTD·Filed 2021·Granted Jul 23, 2024·0 cites·14 claims
- 3357US10916513B2Method and system for providing a reverse engineering resistant hardware embedded security moduleSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Feb 9, 2021·0 cites·20 claims
- 3456US8963210B2Standard cell for integrated circuitSENGUPTA RWIK·Filed 2011·Granted Feb 24, 2015·1 cites·24 claims
- 3554US11182686B24T4R ternary weight cell with high on/off ratio backgroundSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Nov 23, 2021·0 cites·20 claims
- 3651US11354470B1System and method for device placementCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Jun 7, 2022·0 cites·20 claims
- 3748US10424581B2Sub 59 MV/decade SI CMOS compatible tunnel FET as footer transistor for power gatingSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Sep 24, 2019·0 cites·17 claims
- 3848US9929180B2Semiconductor deviceSAMSUNG ELECTRONICS CO LTD·Filed 2017·Granted Mar 27, 2018·0 cites·17 claims
- 3947US10872662B22T2R binary weight cell with high on/off ratio backgroundSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Dec 22, 2020·0 cites·20 claims
- 4047US10868193B2Nanosheet field effect transistor cell architectureSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Dec 15, 2020·0 cites·20 claims
- 4145US10832774B2Variation resistant 3T3R binary weight cell with low output current and high on/off ratioSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Nov 10, 2020·0 cites·20 claims
- 4243US9691860B2Methods of forming defect-free SRB onto lattice-mismatched substrates and defect-free fins on insulatorsSAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted Jun 27, 2017·0 cites·20 claims
- 4342US10297673B2Methods of forming semiconductor devices including conductive contacts on source/drainsKITTL JORGE A·Filed 2015·Granted May 21, 2019·0 cites·20 claims
- 4441US2020201954A1Method of designing a layout for a semiconductor integrated circuitSAMSUNG ELECTRONICS CO LTD·Filed 2019·Application pending·0 cites
- 4536US9728502B2Metal oxysilicate diffusion barriers for damascene metallization with low RC delays and methods for forming the sameSAMSUNG ELECTRONICS CO LTD·Filed 2015·Granted Aug 8, 2017·0 cites·6 claims
- 4628US2016111421A1Multiple cpp for increased source/drain area for fets including in a critical speed pathRODDER MARK S·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →