Inventor · disambiguated record
Ryan Ryoung-Han Kim
Also filed as: KIM RYAN · KIM RYAN RYOUNG-HAN
42 granted patents·9 pending applications·555 citations·filing 2013–2025
98Inventor score
Top patents by PatentIndex Score
51 records- 0199US9412616B1Methods of forming single and double diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting productsGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 9, 2016·148 cites·22 claims
- 0299US9362181B1Methods of forming diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting productsGLOBALFOUNDRIES INC·Filed 2015·Granted Jun 7, 2016·69 cites·31 claims
- 0398US9865704B2Single and double diffusion breaks on integrated circuit products comprised of FinFET devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Jan 9, 2018·41 cites·20 claims
- 0497US9711511B1Vertical channel transistor-based semiconductor memory structureGLOBALFOUNDRIES INC·Filed 2016·Granted Jul 18, 2017·30 cites·16 claims
- 0597US9490317B1Gate contact structure having gate contact layerGLOBALFOUNDRIES INC·Filed 2015·Granted Nov 8, 2016·29 cites·16 claims
- 0696US9209038B2Methods for fabricating integrated circuits using self-aligned quadruple patterningGLOBALFOUNDRIES INC·Filed 2014·Granted Dec 8, 2015·34 cites·20 claims
- 0795US9478462B1SAV using selective SAQP/SADPGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 25, 2016·31 cites·20 claims
- 0894US9484258B1Method for producing self-aligned viasGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 1, 2016·21 cites·20 claims
- 0993US9202918B2Methods of forming stressed layers on FinFET semiconductor devices and the resulting devicesGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 1, 2015·13 cites·16 claims
- 1092US9553028B2Methods of forming reduced resistance local interconnect structures and the resulting devicesGLOBALFOUNDRIES INC·Filed 2014·Granted Jan 24, 2017·14 cites·17 claims
- 1192US9379027B2Method of utilizing trench silicide in a gate cross-couple constructGLOBALFOUNDRIES INC·Filed 2014·Granted Jun 28, 2016·10 cites·6 claims
- 1292US9171764B2Methods for fabricating integrated circuits using self-aligned quadruple patterningGLOBALFOUNDRIES INC·Filed 2013·Granted Oct 27, 2015·14 cites·20 claims
- 1391US9184169B2Methods of forming FinFET devices in different regions of an integrated circuit productGLOBALFOUNDIES INC·Filed 2014·Granted Nov 10, 2015·21 cites·24 claims
- 1490US9651855B2Methods for optical proximity correction in the design and fabrication of integrated circuits using extreme ultraviolet lithographyGLOBALFOUNDRIES INC·Filed 2015·Granted May 16, 2017·7 cites·18 claims
- 1590US9153694B2Methods of forming contact structures on finfet semiconductor devices and the resulting devicesGLOBALFOUNDRIES INC·Filed 2013·Granted Oct 6, 2015·10 cites·21 claims
- 1689US9953834B1Method of making self-aligned continuity cuts in mandrel and non-mandrel metal linesGLOBALFOUNDRIES INC·Filed 2017·Granted Apr 24, 2018·5 cites·10 claims
- 1789US9595478B2Dummy gate used as interconnection and method of making the sameGLOBALFOUNDRIES INC·Filed 2015·Granted Mar 14, 2017·6 cites·12 claims
- 1889US9362403B2Buried fin contact structures on FinFET semiconductor devicesGLOBALFOUNDRIES INC·Filed 2015·Granted Jun 7, 2016·6 cites·17 claims
- 1986US9859120B1Method of making self-aligned continuity cuts in mandrel and non-mandrel metal linesGLOBALFOUNDRIES INC·Filed 2016·Granted Jan 2, 2018·4 cites·10 claims
- 2082US9362279B1Contact formation for semiconductor deviceGLOBALFOUNDRIES INC·Filed 2015·Granted Jun 7, 2016·3 cites·16 claims
- 2182US8796859B2Multilayer interconnect structure and method for integrated circuitsGLOBALFOUNDRIES INC·Filed 2013·Granted Aug 5, 2014·4 cites·6 claims
- 2281US9406616B2Merged source/drain and gate contacts in SRAM bitcellGLOBALFOUNDRIES INC·Filed 2014·Granted Aug 2, 2016·5 cites·21 claims
- 2381US9209037B2Methods for fabricating integrated circuits including selectively forming and removing fin structuresGLOBALFOUNDRIES INC·Filed 2014·Granted Dec 8, 2015·5 cites·19 claims
- 2476US9449835B2Methods of forming features having differing pitch spacing and critical dimensionsGLOBALFOUNDRIES INC·Filed 2015·Granted Sep 20, 2016·2 cites·18 claims
- 2574US10580779B2Vertical transistor static random access memory cellGLOBALFOUNDRIES INC·Filed 2018·Granted Mar 3, 2020·3 cites·20 claims
- 2674US9275889B2Method and apparatus for high yield contact integration schemeGLOBALFOUNDRIES INC·Filed 2013·Granted Mar 1, 2016·3 cites·9 claims
- 2772US10147637B2Methods for forming conductive paths and viasIMEC VZW·Filed 2018·Granted Dec 4, 2018·3 cites·20 claims
- 2871US9543416B2Methods of forming products with FinFET semiconductor devices without removing fins in certain areas of the productGLOBALFOUNDRIES INC·Filed 2014·Granted Jan 10, 2017·2 cites·14 claims
- 2970US9466604B2Metal segments as landing pads and local interconnects in an IC deviceGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 11, 2016·2 cites·20 claims
- 3070US9171934B2Methods of forming semiconductor devices using a layer of material having a plurality of trenches formed thereinGLOBALFOUNDRIES INC·Filed 2014·Granted Oct 27, 2015·2 cites·31 claims
- 3168US10592632B2Method for analyzing design of an integrated circuitIMEC VZW·Filed 2018·Granted Mar 17, 2020·1 cites·18 claims
- 3268US10192792B2Method of utilizing trench silicide in a gate cross-couple constructGLOBALFOUNDRIES INC·Filed 2016·Granted Jan 29, 2019·1 cites·20 claims
- 3368US10153162B2Shrink process aware assist featuresGLOBALFOUNDRIES INC·Filed 2016·Granted Dec 11, 2018·1 cites·17 claims
- 3468US9299781B2Semiconductor devices with contact structures and a gate structure positioned in trenches formed in a layer of materialGLOBALFOUNDRIES INC·Filed 2014·Granted Mar 29, 2016·2 cites·24 claims
- 3564US10050118B2Semiconductor device configured for avoiding electrical shortingGLOBALFOUNDRIES INC·Filed 2014·Granted Aug 14, 2018·1 cites·7 claims
- 3664US9460079B2Method, system and recording medium for providing dictionary function and file distribution systemNAVER CORP·Filed 2015·Granted Oct 4, 2016·1 cites·20 claims
- 3763US9431264B2Methods of forming integrated circuits and multiple critical dimension self-aligned double patterning processesGLOBALFOUNDRIES INC·Filed 2013·Granted Aug 30, 2016·1 cites·19 claims
- 3860US2025322134A1IC Device and a Method for Determining a Floorplan for an IC DeviceIMEC VZW·Filed 2025·Application pending·0 cites
- 3954US10103066B2Method of utilizing trench silicide in a gate cross-couple constructGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 16, 2018·0 cites·18 claims
- 4051US10283505B2Dummy gate used as interconnection and method of making the sameGLOBALFOUNDRIES INC·Filed 2017·Granted May 7, 2019·0 cites·13 claims
- 4148US11270912B2Method for forming a via hole self-aligned with a metal block on a substrateIMEC VZW·Filed 2020·Granted Mar 8, 2022·0 cites·11 claims
- 4248US2015349053A1Semiconductor devices with a layer of material having a plurality of source/drain trenchesGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
- 4347US11092884B2Mask for extreme-ultraviolet (extreme-UV) lithography and method for manufacturing the sameIMEC VZW·Filed 2018·Granted Aug 17, 2021·0 cites·16 claims
- 4447US2016141242A1Method and apparatus for a high yield contact integration schemeGLOBALFOUNDRIES INC·Filed 2016·Application pending·0 cites
- 4546US2016043223A1Finfet semiconductor devices with stressed layersGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
- 4644US10978335B2Method for producing a gate cut structure on an array of semiconductor finsIMEC VZW·Filed 2019·Granted Apr 13, 2021·0 cites·20 claims
- 4743US2025300074A1Semiconductor deviceIMEC VZW·Filed 2025·Application pending·0 cites
- 4843US2015318288A1Vertical transistor static random access memory cellGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 4940US2015097249A1Cross coupling gate using mulitple patterningGLOBALFOUNDRIES INC·Filed 2013·Application pending·0 cites
- 5035US2017358585A1Method, apparatus and system for fabricating self-aligned contact using block-type hard maskGLOBALFOUNDRIES INC·Filed 2016·Application pending·0 cites
Showing the top 50 of 51 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →