Inventor · disambiguated record
Sachin Ramesh Gugwad
Also filed as: GUGWAD SACHIN · GUGWAD SACHIN RAMESH
10 granted patents·29 citations·filing 2016–2023
85Inventor score
Files withCADENCE DESIGN SYSTEMS INC10
Top patents by PatentIndex Score
10 records- 0193US11483185B1Hardware efficient decision feedback equalization trainingCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Oct 25, 2022·4 cites·20 claims
- 0293US11323296B1Decision feedback equalization training scheme for GDDR applicationsCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted May 3, 2022·4 cites·20 claims
- 0391US12205673B1Read data strobe path having variation compensation and delay linesCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Jan 21, 2025·3 cites·20 claims
- 0485US12183427B1System and method for write clock double data rate duty cycle correctionCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Dec 31, 2024·1 cites·18 claims
- 0585US10771108B1Crosstalk cancellation in a receiverCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Sep 8, 2020·6 cites·20 claims
- 0682US11979262B1Identifying and training floating tap for decision feedback equalizationCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted May 7, 2024·1 cites·20 claims
- 0781US11580048B1Reference voltage training schemeCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Feb 14, 2023·3 cites·20 claims
- 0878US11277285B1Continuous time linear equalization system and methodCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Mar 15, 2022·2 cites·20 claims
- 0978US9754646B1Voltage stress tolerant high speed memory driver having flying capacitor circuitCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Sep 5, 2017·5 cites·19 claims
- 1068US12413213B1Efficient clocking structures for high-speed systems using hybrid digital delay lanesCADENCE DESIGN SYSTEMS INC·Filed 2023·Granted Sep 9, 2025·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →