Inventor · disambiguated record
Sankaranarayanan Srinivasan
Also filed as: SRINIVASAN SANKARANARAYANAN
17 granted patents·205 citations·filing 2003–2022
94Inventor score
Technology areasG06F
Top patents by PatentIndex Score
17 records- 0192US7657855B1Efficient timing graph update for dynamic netlist changesXILINX INC·Filed 2007·Granted Feb 2, 2010·57 cites·20 claims
- 0288US11853662B2Machine-learning enhanced compilerSYNOPSYS INC·Filed 2022·Granted Dec 26, 2023·3 cites·17 claims
- 0386US7984415B1Merging of equivalent logic blocks in a circuit designXILINX INC·Filed 2009·Granted Jul 19, 2011·18 cites·19 claims
- 0483US7979831B1Placement driven control set resynthesisXILINX INC·Filed 2008·Granted Jul 12, 2011·14 cites·18 claims
- 0582US7392498B1Method and apparatus for implementing a pre-implemented circuit design for a programmable logic deviceXILINX INC·Filed 2004·Granted Jun 24, 2008·41 cites·19 claims
- 0681US8024696B1Clock speed for a digital circuitXILINX INC·Filed 2008·Granted Sep 20, 2011·11 cites·20 claims
- 0778US8010923B1Latch based optimization during implementation of circuit designs for programmable logic devicesXILINX INC·Filed 2008·Granted Aug 30, 2011·7 cites·16 claims
- 0874US8136073B1Circuit design fittingSRINIVASAN SANKARANARAYANAN·Filed 2009·Granted Mar 13, 2012·9 cites·20 claims
- 0973US11366948B2Machine-learning enhanced compilerSYNOPSYS INC·Filed 2020·Granted Jun 21, 2022·1 cites·13 claims
- 1070US7636876B1Cost-based performance driven legalization technique for placement in logic designsXILINX INC·Filed 2006·Granted Dec 22, 2009·5 cites·20 claims
- 1169US7181704B1Method and system for designing integrated circuits using implementation directivesXILINX INC·Filed 2004·Granted Feb 20, 2007·15 cites·14 claims
- 1263US8141010B1Method and arrangement providing for implementation granularity using implementation setsKONG RAYMOND·Filed 2008·Granted Mar 20, 2012·2 cites·16 claims
- 1363US7853914B1Fanout-optimization during physical synthesis for placed circuit designsXILINX INC·Filed 2007·Granted Dec 14, 2010·3 cites·14 claims
- 1460US7152217B1Alleviating timing based congestion within circuit designsXILINX INC·Filed 2004·Granted Dec 19, 2006·8 cites·21 claims
- 1559US7360177B1Method and arrangement providing for implementation granularity using implementation setsXILINX INC·Filed 2004·Granted Apr 15, 2008·5 cites·13 claims
- 1658US7076758B1Using router feedback for placement improvements for logic designXILINX INC·Filed 2003·Granted Jul 11, 2006·6 cites·22 claims
- 1748US8146041B1Latch based optimization during implementation of circuit designs for programmable logic devicesSRINIVASAN SANKARANARAYANAN·Filed 2011·Granted Mar 27, 2012·0 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →