Inventor · disambiguated record
Sarasvathi Thangaraju
Also filed as: THANGARAJU SARASVATHI
8 granted patents·11 citations·filing 2012–2016
79Inventor score
Files withGLOBALFOUNDRIES INC8
Top patents by PatentIndex Score
8 records- 0176US8907496B1Circuit structures and methods of fabrication with enhanced contact via electrical connectionGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 9, 2014·4 cites·20 claims
- 0267US9455188B2Through silicon via device having low stress, thin film gaps and methods for forming the sameGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 27, 2016·2 cites·11 claims
- 0364US9245790B2Integrated circuits and methods of forming the same with multiple embedded interconnect connection to same through-semiconductor viaGLOBALFOUNDRIES INC·Filed 2013·Granted Jan 26, 2016·2 cites·8 claims
- 0459US9236301B2Customized alleviation of stresses generated by through-substrate via(S)GLOBALFOUNDRIES INC·Filed 2013·Granted Jan 12, 2016·1 cites·17 claims
- 0558US9761481B2Integrated circuits and methods of forming the same with metal layer connection to through-semiconductor viaGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 12, 2017·2 cites·7 claims
- 0657US9658531B2Semiconductor device resolution enhancement by etching multiple sides of a maskGLOBALFOUNDRIES INC·Filed 2014·Granted May 23, 2017·0 cites·11 claims
- 0754US8895211B2Semiconductor device resolution enhancement by etching multiple sides of a maskGLOBALFOUNDRIES INC·Filed 2012·Granted Nov 25, 2014·0 cites·17 claims
- 0851US10043764B2Through silicon via device having low stress, thin film gaps and methods for forming the sameGLOBALFOUNDRIES INC·Filed 2016·Granted Aug 7, 2018·0 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →