Inventor · disambiguated record
Sanjay Vishin
Also filed as: VISHIN SANJAY
30 granted patents·1 pending application·1,354 citations·filing 1996–2018
97Inventor score
Top patents by PatentIndex Score
31 records- 0194US7853777B2Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructionsMIPS TECH INC·Filed 2005·Granted Dec 14, 2010·43 cites·38 claims
- 0292US7752627B2Leaky-bucket thread scheduler in a multithreading microprocessorMIPS TECH INC·Filed 2005·Granted Jul 6, 2010·34 cites·39 claims
- 0391US6098089AGeneration isolation system and method for garbage collectionSUN MICROSYSTEMS INC·Filed 1997·Granted Aug 1, 2000·175 cites·31 claims
- 0490US7664936B2Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stagesMIPS TECH INC·Filed 2005·Granted Feb 16, 2010·26 cites·72 claims
- 0589US5873104ABounded-pause time garbage collection system and method including write barrier associated with source and target instances of a partially relocated objectSUN MICROSYSTEMS INC·Filed 1997·Granted Feb 16, 1999·116 cites·38 claims
- 0688US7774549B2Horizontally-shared cache victims in multiple core processorsMIPS TECH INC·Filed 2007·Granted Aug 10, 2010·17 cites·11 claims
- 0788US7657891B2Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiencyMIPS TECH INC·Filed 2005·Granted Feb 2, 2010·18 cites·39 claims
- 0888US5857210ABounded-pause time garbage collection system and method including read and write barriers associated with an instance of a partially relocated objectSUN MICROSYSTEMS INC·Filed 1997·Granted Jan 5, 1999·103 cites·54 claims
- 0988US5845298AWrite barrier system and method for trapping garbage collection page boundary crossing pointer storesSUN MICROSYSTEMS INC·Filed 1997·Granted Dec 1, 1998·146 cites·26 claims
- 1086US5873105ABounded-pause time garbage collection system and method including write barrier associated with a source instance of a partially relocated objectSUN MICROSYSTEMS INC·Filed 1997·Granted Feb 16, 1999·128 cites·49 claims
- 1186US5860146AAuxiliary translation lookaside buffer for assisting in accessing data in remote address spacesSUN MICROSYSTEMS INC·Filed 1996·Granted Jan 12, 1999·131 cites·12 claims
- 1285US5953736AWrite barrier system and method including pointer-specific instruction variant replacement mechanismSUN MICROSYSTEMS INC·Filed 1997·Granted Sep 14, 1999·121 cites·40 claims
- 1384US7721127B2Multithreaded dynamic voltage-frequency scaling microprocessorMIPS TECH INC·Filed 2006·Granted May 18, 2010·13 cites·46 claims
- 1483US5930807AApparatus and method for fast filtering read and write barrier operations in garbage collection systemSUN MICROSYSTEMS INC·Filed 1997·Granted Jul 27, 1999·108 cites·20 claims
- 1581US6178479B1Cycle-skipping DRAM for power savingNBAND COMM·Filed 1999·Granted Jan 23, 2001·51 cites·20 claims
- 1680US7644237B1Method and apparatus for global ordering to insure latency independent coherenceMIPS TECH INC·Filed 2004·Granted Jan 5, 2010·25 cites·49 claims
- 1779US8151268B2Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiencyJONES DARREN M·Filed 2010·Granted Apr 3, 2012·7 cites·16 claims
- 1874US7594089B2Smart memory based synchronization controller for a multi-threaded multiprocessor SoCMIPS TECH INC·Filed 2004·Granted Sep 22, 2009·20 cites·69 claims
- 1973US8009090B2System and method for dynamic voltage scaling in a GPS receiverSIRF TECH INC·Filed 2009·Granted Aug 30, 2011·11 cites·54 claims
- 2066US10284475B2Distributed leaky bucket based multi-modem scheduler for multimedia streamsQUALCOMM INC·Filed 2017·Granted May 7, 2019·1 cites·56 claims
- 2160US8037253B2Method and apparatus for global ordering to insure latency independent coherenceMIPS TECH INC·Filed 2009·Granted Oct 11, 2011·1 cites·20 claims
- 2260US6311280B1Low-power memory system with incorporated vector processingNBAND COMM·Filed 1999·Granted Oct 30, 2001·40 cites·13 claims
- 2358US8725950B2Horizontally-shared cache victims in multiple core processorsVISHIN SANJAY·Filed 2010·Granted May 13, 2014·1 cites·15 claims
- 2453US7769957B2Preventing writeback race in multiple core processorsMIPS TECH INC·Filed 2007·Granted Aug 3, 2010·2 cites·19 claims
- 2549US10601710B2IP level multipath protocolQUALCOMM INC·Filed 2018·Granted Mar 24, 2020·0 cites·29 claims
- 2647US7739455B2Avoiding livelock using a cache manager in multiple core processorsMIPS TECH INC·Filed 2007·Granted Jun 15, 2010·0 cites·21 claims
- 2743US10609529B2Multi-modem scheduler for multimedia streamsQUALCOMM INC·Filed 2017·Granted Mar 31, 2020·0 cites·32 claims
- 2840US5761722AMethod and apparatus for solving the stale data problem occurring in data access performed with data cachesSUN MICROSYSTEMS INC·Filed 1997·Granted Jun 2, 1998·12 cites·12 claims
- 2939US10779194B2Preferred path network scheduling in multi-modem setupQUALCOMM INC·Filed 2018·Granted Sep 15, 2020·0 cites·14 claims
- 3039US2019132555A1Methods and systems to broadcast sensor outputs in an automotive environmentQUALCOMM INC·Filed 2018·Application pending·0 cites
- 3132US6219757B1Cache flush operation for a stack-based microprocessorSUN MICROSYSTEMS INC·Filed 1998·Granted Apr 17, 2001·4 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →